Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
127
8.2.2.9 SLCAP — Slot Capabilities
8.2.2.10 SLCTL — Slot Control
Table 158. Offset 54h: SLCAP — Slot Capabilities
Size: 32 bit Default: 00000060h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
54h
57h
Bit Range Default Access Acronym Description
31 : 19 0000h RWO PSN
Physical Slot Number: This is a value that is unique to the slot number.
The BIOS sets this field and it remains set until a platform reset.
18 : 17 00b RO RSVD Reserved
16 : 15 00b RWO SLS
Slot Power Limit Scale: This specifies the scale used for the slot power
limit value. The BIOS sets this field and it remains set until a platform
reset.
14 : 07 00h RWO SLV
Slot Power Limit Value: This specifies the upper limit (in conjunction
with SLS value), on the upper limit on power supplied by the slot. The
two values together indicate the amount of power in watts allowed for
the slot. The BIOS sets this field, and it remains set until a platform
reset.
06 1b RO HPC Hot Plug Capable: This indicates that hot plug is supported.
05 1b RO HPS
Hot Plug Surprise: This indicates that the device may be removed from
the slot without prior notification.
04 0b RO PIP
Power Indicator Present: This indicates that a power indicator LED is
not present for this slot.
03 0b RO AIP
Attention Indicator Present: This indicates that an attention indicator
LED is not present for this slot.
02 0b RO MSP MRL Sensor Present: This indicates that an MRL sensor is not present.
01 0b RO PCP
Power Controller Present: This indicates that a power controller is not
implemented for this slot.
00 0b RO ABP
Attention Button Present: This indicates that an attention button is not
implemented for this slot.
Table 159. Offset 58h: SLCTL — Slot Control (Sheet 1 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
58h
59h
Bit Range Default Access Acronym Description
15 : 13 0h RO RSVD Reserved
12 0b RW LACE
Link Active Changed Enable: When set, this field enables generation of
a hot plug interrupt when the Data Link Layer Link Active field is
changed.
11 : 10 0b RO RSVD Reserved
09 : 08 00b RW PIC Power Indicator Control: PIC is not supported
07 : 06 00b RW AIC Attention Indicator Control: AIC is not supported
05 0b RW HPE
Hot Plug Interrupt Enable: When set, enables generation of a hot plug
interrupt on enabled hot plug events.
04 0b RO CCE Command Completed Interrupt Enable: CCE is not supported