Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
126
8.2.2.7 LCTL — Link Control
8.2.2.8 LSTS — Link Status
Table 156. Offset 50h: LCTL — Link Control
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
50h
51h
Bit Range Default Access Acronym Description
15 : 0 RO RSVD Reserved
07 0b RW ES
Extended Synch: When set, this forces extended transmission of FTS
ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0.
06 0b RW CCC
Common Clock Configuration: When set, this indicates that the
processor and device are operating with a distributed common reference
clock.
05 0b RO/W RL
Retrain Link: When set, the root port will train its downstream link. This
bit always returns ‘0’ when read. Software uses LSTS.LT and LSTS.LTE to
check the status of training.
04 0b RW LD Link Disable: When set, the root port will disable the link.
03 0b RO RCBC
Read Completion Boundary Control: Read completion boundary is 64
bytes.
02 0b RO RSVD Reserved
01 : 00 0h RW APMC
Active State Link PM Control: This indicates if the root port should
enter L0s or L1 or both.
00 = Disabled (The processor does not support disable mode; writing 00
has no effect.)
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled
Table 157. Offset 52h: LSTS — Link Status
Size: 16 bit Default: 1001h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
52h
53h
Bit Range Default Access Acronym Description
13 0 RO LA
Link Active: This is set to 1b when the Data Link Control and
Management State Machine is in the DL_Active state; it is 0b otherwise.
12 1 RO SCC
Slot Clock Configuration: The processor uses the same reference clock
as on the platform and does not generate its own clock.
11 0 RO LT
Link Training: The root port sets this bit whenever link training is
occurring. It clears the bit on completion of link training.
10 0 RO LTE Link Training Error: Not supported
09 : 04 00h RO NLW
Negotiated Link Width: This may only take the value of a single link
(01h). The value of this register is undefined if the link has not
successfully trained.
03 : 00 1h RO LS Link Speed: Link is 2.5 Gb/s.