Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
125
8.2.2.5 DSTS — Device Status
8.2.2.6 LCAP — Link Capabilities
Table 154. Offset 4Ah: DSTS — Device Status
Size: 16 bit Default: 0010h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
4Ah
4Bh
Bit Range Default Access Acronym Description
15 : 06 0 RO RSVD Reserved
05 0 RO TDP
Transactions Pending: This bit has no meaning for the root port since
only one transaction may be pending to the processor. A read of this
cannot occur until it has already returned to ‘0.’
04 1 RO APD AUX Power Detected: The root port contains AUX power for wake-up.
03 0 RWC URD
Unsupported Request Detected: This indicates that an unsupported
request was detected.
02 0 RWC FED
Fatal Error Detected: This indicates that a fatal error was detected. It is
set when a fatal error occurred on from a data link protocol error, buffer
overflow, or malformed TLP.
01 0 RWC NFED
Non-Fatal Error Detected: This indicates that a non-fatal error was
detected. It is set when an received a non-fatal error occurred from a
poisoned TLP, unexpected completions, unsupported requests, completer
abort, or completer time-out.
00 0 RWC CED
Correctable Error Detected: This indicates that a correctable error was
detected. It is set when received an internal correctable error from
receiver errors / framing errors, TLP CRC error, DLLP CRC error, replay
num. rollover, or replay time-out.
Table 155. Offset 4Ch: LCAP — Link Capabilities
Size: 32 bit Default: XX154C11h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
4Ch
4Fh
Bit Range Default Access Acronym Description
31 : 24
01h,
02h,
03h or
04h
RO PN
Port Number: This indicates the port number for the root port. This
value is different for each implemented port. Port 0 reports 01h. Port 1
reports 02h. Port 2 reports 03h. Port 3 reports 04h.
23 : 21 0b RO RSVD Reserved
20 1b RO LARC
Link Active Reporting Capable: This port supports the optional
capability of reporting the DL_Active state of the Data Link Control and
Management State Machine.
19 0b RO RSVD Reserved
18 1b RO CPM
Clock Power Management: This indicates that clock power
management is supported.
17 : 15 010b RO EL1 L1 Exit Latency: This indicates an exit latency of 2 µs to 4 µs.
14 : 12 100h RO EL0
L0s Exit Latency: This indicates an exit latency based on common-clock
configuration. When cleared, it uses MPC.UCEL. When set, it uses
MPC.CCEL
11 : 10 3h RO APMS
Active State Link PM Support: This indicates that both L0s and L1 are
supported.
09 : 04 01h RO MLW Maximum Link Width: May only be a single lane
03 : 00 1h RO MLS Maximum Link Speed: This indicates that the link speed is 2.5 Gb/s