Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
124
8.2.2.4 DCTL — Device Control
11 : 09 111b RO E1AL
Endpoint L1 Acceptable Latency: This indicates more than 4 µs. This
field essentially has no meaning for root ports since root ports are not
endpoints.
08 : 06 111b RO E0AL
Endpoint L0 Acceptable Latency: This indicates more than 64 µs. This
field essentially has no meaning for root ports since root ports are not
endpoints.
05 0b RO ETFS
Extended Tag Field Supported: This bit indicates that 5-bit tag fields
are supported.
04 : 03 00b RO PFS Phantom Functions Supported: No phantom functions supported
02 : 00 000b RO MPS
Max Payload Size Supported: This indicates that the maximum
payload size supported is 128B.
Table 153. Offset 48h: DCTL — Device Control
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
48h
49h
Bit Range Default Access Acronym Description
15 0b RO RSVD Reserved
14 : 12 000b RO MRRS Max Read Request Size: Hardwired to 0
11 0b RO ENS
Enable No Snoop: Not supported. The root port will never issue non-
snoop requests.
10 0b RW APME
AUX Power PM Enable: This must be RW for OS testing. The OS will set
this bit to ‘1’ if the device connected has detected AUX power. It has no
effect on the root port otherwise.
09 0b RO PFE Phantom Functions Enable: Not supported
08 0b RO ETFE Extended Tag Field Enable: Not supported
07 : 05 000b RW MPS
Max Payload Size: The root port only supports 128B payloads,
regardless of the programming of this field.
04 0b RO ERO Enable Relaxed Ordering: Not supported
03 0b RW URE
Unsupported Request Reporting Enable: When set, the root port will
generate errors when detecting an unsupported request.
02 0b RW FEE
Fatal Error Reporting Enable: When set, the root port will generate
errors when detecting a fatal error. When cleared, the root port will
ignore fatal errors.
01 0b RW NFE
Non-Fatal Error Reporting Enable: When set, the root port will
generate errors when detecting a non-fatal error. When cleared, the root
port will ignore non-fatal errors.
00 0b RW CEE
Correctable Error Reporting Enable: When set, the root port will
generate errors when detecting a correctable error. When cleared, the
root port will ignore correctable errors.
Table 152. Offset 44h: DCAP — Device Capabilities (Sheet 2 of 2)
Size: 32 bit Default: 00008FC0h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
44h
47h
Bit Range Default Access Acronym Description