Datasheet
PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
122
8.2.2 Root Port Capability Structure
The following registers follow the PCI Express* capability list structure as defined in the
PCI Express* specification, to indicate the capabilities of the root interconnect.
05 0b RO MAM Master Abort Mode: Reserved per PCI Express* spec.
04 0b RW V16
VGA 16-Bit Decode: When set, this indicates that the I/O aliases of the
VGA range (see BCTRL.VE definition below) are not enabled and only the
base I/O ranges can be decoded.
03 0b RW VE
VGA Enable: When set, the following ranges will be claimed off the
backbone by the root port:
• Memory ranges A0000h-BFFFFh
• I/O ranges 3B0h–3BBh and 3C0h–3DFh, and all aliases of bits 15:10
in any combination of 1s
02 0b RW IE
ISA Enable: This bit only applies to I/O addresses that are enabled by
the I/O Base and I/O Limit registers and are in the first 64 kB of PCI I/O
space. If this bit is set, the root port will block any forwarding from the
backbone to the device of I/O transactions addressing the last 768 bytes
in each 1 kB block (offsets 100h to 3FFh).
01 0b RW SE
SERR_B Enable: When set, ERR_COR, ERR_NONFATAL, and ERR_FATAL
messages received are forwarded to the backbone. When cleared, they
are not.
00 0b RW PERE
Parity Error Response Enable: When set, poisoned write TLPs and
completions indicating poisoned TLPs will set the SSTS.DPD.
Table 148. Offset 3Eh: BCTRL — Bridge Control (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
3Eh
3Fh
Bit Range Default Access Acronym Description
Table 149. Root Port Capability Structure
Start End Symbol Register Name
42 43 XCAP PCI Express* Capabilities
44 47 DCAP Device Capabilities
48 49 DCTL Device Control
4A 4B DSTS Device Status
4C 4F LCAP Link Capabilities
50 51 LCTL Link Control
52 53 LSTS Link Status
54 57 SLCAP Slot Capabilities
58 59 SLCTL Slot Control
5A 5B SLSTS Slot Status
5C 5D RCTL Root Control
5E 5F RCAP Root Capabilities
60 63 RSTS Root Status
64 65 LCTL2 Link Control 2
66 67 LSTS2 Link Status 2