Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
121
8.2.1.21 IPIN — Interrupt Pin
This register specifies which interrupt pin this device uses.
8.2.1.22 BCTRL — Bridge Control
This register provides extensions to the PCICMD1 register that are specific to PCI-to-
PCI bridges. The BCTRL provides additional control for the secondary interface as well
as some bits that effect the overall behavior of the “virtual” Host-PCI Express* bridge
embedded within the processor, for example, VGA compatible address ranges mapping.
Table 146. Offset 3Ch: ILINE — Interrupt Line
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
3Ch
3Ch
Bit Range Default Access Acronym Description
07 : 00 00h RW ILINE
Interrupt Line: This software written value indicates to which interrupt
line (vector) the interrupt is connected. No hardware action is taken on
this register.
Table 147. Offset 3Dh: IPIN — Interrupt Pin
Size: 8 bit Default: 01h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
3Dh
3Dh
Bit Range Default Access Acronym Description
07 : 00 01h RO IPIN
Interrupt Pin (IPIN): This indicates the interrupt pin driven by the root
port. At reset, this register takes on the following values, which reflect
the reset state of the D23/24/25/26IP register in chipset configuration
space:
Port Bits[15:12] Bits[11:08]
0 0h D23IP.P1IP
1 0h D24IP.P1IP
2 0h D25IP.P1IP
3 0h D26IP.P1IP
The value that is programmed into Interrupt Pin Configuration register is
always reflected in this register.
Table 148. Offset 3Eh: BCTRL — Bridge Control (Sheet 1 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
3Eh
3Fh
Bit Range Default Access Acronym Description
15 : 12 0h RO RSVD Reserved
11 0b RO DTSE Discard Timer SERR_B Enable: Reserved per PCI Express* spec.
10 0b RO DTS Discard Timer Status: Reserved per PCI Express* spec.
09 0b RO SDT Secondary Discard Timer: Reserved per PCI Express* spec.
08 0b RO PDT Primary Discard Timer: Reserved per PCI Express* spec.
07 0b RO FBE Fast Back to Back Enable: Reserved per PCI Express* spec.
06 0b RW SBR
Secondary Bus Reset: This triggers a Hot Reset on the PCI Express*
port.