Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
120
8.2.1.18 PML — Prefetchable Memory Limit Address
This register controls the CPU to PCI Express* prefetchable memory access routing
based on the following formula: PREFETCHABLE_MEMORY_BASE =< address =<
PREFETCHABLE_MEMORY_LIMIT. The upper 12 bits of this register are read/write and
correspond to address bits A[31:20] of the 32-bit address. This register must be
initialized by the configuration software. For the purpose of address decode, address
bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address
range will be at the top of a 1 MB aligned memory block. Note that prefetchable
memory range is supported to allow segregation by the configuration software between
the memory ranges that must be defined as UC and the ones that can be designated as
USWC (in other words, prefetchable) from the CPU perspective.
8.2.1.19 CAPP — Capabilities Pointer
The capabilities pointer provides the address offset to the location of the first entry in
this device’s linked list of capabilities.
8.2.1.20 ILINE — Interrupt Line
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Table 143. Offset 24h: PMB — Prefetchable Memory Base Address
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
24h
25h
Bit Range Default Access Acronym Description
15 : 04 000h RW PMB
Prefetchable Memory Base Address: This corresponds to A[31:20] of
the lower limit of the memory range that will be passed to PCI Express*.
03 : 00 0h RW RSVD Reserved
Table 144. Offset 26h: PML — Prefetchable Memory Limit Address
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
26h
27h
Bit Range Default Access Acronym Description
15 : 04 000h RW PML
Prefetchable Memory Address Limit: This corresponds to A[31:20] of
the upper limit of the address range passed to PCI Express*.
03 : 00 0h RW RSVD Reserved
Table 145. Offset 34h: CAPP — Capabilities Pointer
Size: 8 bit Default: 40h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
34h
34h
Bit Range Default Access Acronym Description
07 : 00 40h RO PTR
First Capability: The first capability in the list is the Subsystem ID and
Subsystem Vendor ID Capability.