Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
118
8.2.1.13 IOLIMIT — I/O Limit Address
This register controls the CPU to PCI Express* I/O access routing based on the
following formula: IO_BASE =< address =< IO_LIMIT. Only the upper four bits are
programmable. For the purpose of address decode, address bits A[11:0] are assumed
to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4 kB
aligned address block.
8.2.1.14 SSTS — Secondary Status
SSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side of the “virtual” PCI-to-PCI bridge embedded within the
processor.
Table 139. Offset 1Dh: IOLIMIT — I/O Limit Address
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
1Dh
1Dh
Bit Range Default Access Acronym Description
07 : 04 0h RW IOLA
I/O Address Limit: I/O Base bits corresponding to address lines 15:12
for 4 kB alignment. Bits 11:0 are assumed to be padded to FFFh.
Devices between this upper limit and IOBASE will be passed to the PCI
Express* hierarchy associated with this device.
03 : 00 0h RO IOLC
I/O Limit Address Capability: Indicates that the bridge does not
support 32-bit I/O addressing.
Table 140. Offset 1Eh: SSTS — Secondary Status (Sheet 1 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
1Eh
1Fh
Bit Range Default Access Acronym Description
15 0b RWC DPE
Detected Parity Error: This bit is set by the Secondary Side for a Type
1 Configuration Space header device whenever it receives a Poisoned
TLP, regardless of the state of the Parity Error Response Enable bit in the
Bridge Control Register.
14 0b RWC RSE
Received System Error: This bit is set when the Secondary Side for a
Type 1 configuration space header device receives an ERR_FATAL or
ERR_NONFATAL.
13 0b RWC RMA
Received Master Abort: This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the
Type 1 Header Device itself) receives a Completion with Unsupported
Request Completion Status.
12 0b RWC RTA
Received Target Abort: This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the
Type 1 Header Device itself) receives a Completion with Completer Abort
Completion Status.
11 0b RO STA
Signaled Target Abort: Not applicable or implemented — hardwired to
0. The processor does not generate Target Aborts (the processor will
never complete a request using the Completer Abort Completion status).
10 : 09 00b RO SDTS
Secondary DEVSEL_B Timing Status: Reserved per PCI Express*
Base Specification
08 0b RWC DPD
Data Parity Error Detected: When set, this indicates that the MCH
received across the link (upstream) a Read Data Completion Poisoned
TLP (EP=1). This bit can only be set when the Parity Error Enable bit
BCTRL.PERE in the Bridge Control register is set.