Datasheet
PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
117
8.2.1.11 SBBN — Subordinate Bus Number
This register identifies the subordinate bus (if any) that resides at the level below the
PCI Express* device. This number is programmed by the PCI configuration software to
allow mapping of configuration cycles to the PCI Express* device.
8.2.1.12 IOBASE — I/O Base Address
This register controls the CPU to PCI Express* I/O access routing based on the
following formula: IO_BASE =< address =< IO_LIMIT. Only the upper four bits are
programmable. For the purpose of address decode, address bits A[11:0] are treated as
0. Thus, the bottom of the defined I/O address range will be aligned to a 4 kB
boundary.
Table 136. Offset 19h: SCBN — Secondary Bus Number
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
19h
19h
Bit Range Default Access Acronym Description
07 : 00 00h RW SCBN
Secondary Bus Number: This field is programmed by configuration
software with the bus number assigned to the PCI Express* device.
Table 137. Offset 1Ah: SBBN — Subordinate Bus Number
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
1Ah
1Ah
Bit Range Default Access Acronym Description
07 : 00 00h RW SBBN
Subordinate Bus Number: This register is programmed by
configuration software with the number of the highest subordinate bus
that lies behind the device bridge. When only a single PCI device resides
on the segment, this register will contain the same value as the SCBN
register.
Table 138. Offset 1Ch: IOBASE — I/O Base Address
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
1Ch
1Ch
Bit Range Default Access Acronym Description
07 : 04 0h RW IOBA
I/O Base Address: I/O Base bits corresponding to address lines 15:12
for 4 kB alignment. Bits 11:0 are assumed to be padded to 000h. The
BIOS must not set this register to 00h; otherwise, 0CF8h/0CFCh
accesses will be forwarded to the PCI Express* hierarchy associated with
this device.
03 : 00 0h RO IOBC
I/O Base Address Capability: The bridge does not support 32-bit I/O
addressing.