Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
116
8.2.1.7 CLS — Cache Line Size
8.2.1.8 HTYPE — Header Type
This register identifies the header layout of the configuration space. No physical
register exists at this location.
8.2.1.9 PBN — Primary Bus Number
This register identifies that this “virtual” Host-PCI Express* bridge is connected to PCI
bus #0.
8.2.1.10 SCBN — Secondary Bus Number
This register identifies the bus number assigned to the second bus side of the “virtual”
bridge, in other words, to the PCI Express* device. This number is programmed by the
PCI configuration software to allow mapping of configuration cycles to the PCI Express*
device.
Table 133. Offset 0Ch: CLS — Cache Line Size
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
Ch
Ch
Bit Range Default Access Acronym Description
07 : 00 00h RW CLS
Cache Line Size: Implemented by PCI Express* devices as a read-write
field for legacy compatibility purposes but has no impact on any PCI
Express* device functionality.
Table 134. Offset 0Eh: HTYPE — Header Type
Size: 8 bit Default: 01h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
Eh
Eh
Bit Range Default Access Acronym Description
07 : 00 01h RO HDR
Header Type Register: Returns 01h to indicate that this is a single
function device with a bridge header layout.
Table 135. Offset 18h: PBN — Primary Bus Number
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
18h
18h
Bit Range Default Access Acronym Description
07 : 00 00h RW PBN
Primary Bus Number: Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since
the device is an internal device, its primary bus is always 0.