Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
114
8.2.1.3 CMD — PCI Command
8.2.1.4 PSTS — Primary Status
This register reports the occurrence of error conditions associated with the primary side
of the “virtual” Host-PCI Express* bridge embedded within the processor.
Table 128. Offset 02h:
DID — Device Identification
Size: 16 bit Default: Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
2h
3h
Bit Range Default Access Acronym Description
15 : 00 RO DID(UB)
Device Identification Number: Identifier assigned to the device
(virtual PCI-to-PCI bridge)
PCIe* Device 23 = 8184h
PCIe* Device 24 = 8185h
PCIe* Device 25 = 8180h
PCIe* Device 26 = 8181h
Table 129. Offset 04h: CMD — PCI Command
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
4h
5h
Bit Range Default Access Acronym Description
15 : 11 00h RO RSVD Reserved
10 0b RW ID
Interrupt Disable: This disables pin-based INTx_B interrupts on
enabled hot plug and power management events. When set, internal
INTx_B messages will not be generated. When cleared, internal INTx_B
messages are generated if there is an interrupt for hot plug or power
management.
This bit does not effect interrupt forwarding from devices connected to
the root port. Assert_INTx and Deassert_INTx messages will still be
forwarded to the internal interrupt controllers if this bit is set.
09 0b RO RSVD Reserved
08 0b RW SEE
SERR_B Enable: When set, this enables the root port to generate
SERR_B when PSTS.SSE is set.
07 : 03 00000b RO RSVD Reserved
02 0b RW BME
Bus Master Enable: When set, allows the root port to forward cycles
onto the backbone from a PCI Express* device. When cleared, all cycles
from the device are master aborted.
01 0b RW MSE
Memory Space Enable: When set, memory cycles within the range
specified by the memory base and limit registers can be forwarded to the
PCI Express* device. When cleared, these memory cycles are master
aborted on the backbone.
00 0b RW IOSE
I/O Space Enable: When set, I/O cycles within the range specified by
the I/O base and limit registers can be forwarded to the PCI Express*
device. When cleared, these cycles are master aborted on the backbone.