Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
112
If RCTL.PIE is set, an interrupt is generated. If RCTL.PIE is not set, an SCI/SMI_B may
be set. If RSTS.PS is set, and RCTL.PIE is later written from a ‘0’ to a ‘1,’ an interrupt is
generated.
8.1.2.4 SMI/SCI Generation
To support power management on non PCI Express* aware operating systems, power
management events can be routed to generate SCI, by setting MPC.PMCE. In addition,
RTSTS.PS and PMCES.PME must be set and root port must be in D3hot power state (by
setting PMCS.PS) to generate SCI. When set, a power management event causes
SMSCS.PMCS to be set. BIOS workarounds for power management are supported by
setting MPC.PMME. When set, power management events set SMSCS.PMMS, and
SMI_B is generated. This bit is set regardless of whether interrupts or SCI are enabled.
The SMI_B may occur concurrently with an interrupt or SCI.
8.1.3 Additional Clarifications
8.1.3.1 Non-Snoop Cycles Are Not Supported
The processor does not support No Snoop cycles on PCIe*. DCTL.ENS can never be set.
Platform BIOS must disable generation of these cycles in all installed PCIe* devices.
Generation of a No Snoop request by a PCIe* device may result in a protocol violation
and lead to errors.
For example, a no-snoop read by a device may be returned by a snooped completion,
and this attribute difference, a violation of the specification, will cause the device to
ignore the completion.
8.2 PCI Express* Configuration Registers
8.2.1 PCI Type 1 Bridge Header
Table 126. PCI Type 1 Bridge Header (Sheet 1 of 2)
Register Name Register
Symbol
Register Start Register End Default Value Access
Vendor
Identification
VID 0 1 8086h RO;
Device
Identification
DID 2 3 RO;
PCI Command CMD 4 5 0000h RO; RW;
PCI Status PSTS 6 7 0010h RO; RWC;
Revision
Identification
RID 8 8
01h (for B-0
Stepping)
02h (for B-1
Stepping)
RO;
Class Code CC 9 B 060400h RO;
Cache Line Size CLS C C 00h RW;
Header Type HTYPE E E 01h RO;
Primary Bus
Number
PBN 18 18 00h RW;
Secondary Bus
Number
SCBN 19 19 00h RW;