Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
111
8.0 PCI Express*
8.1 Functional Description
There are four PCI Express* root ports available in the Intel
®
Atom™ Processor E6xx
Series. They reside in device 23, 24, 25, and 26, and all take function 0. Port 0 is
device 23, Port 1 is device 24, Port 2 is device 25 and Port 3 is device 26.
8.1.1 Interrupt Generation
The processor generates interrupts on behalf of hot plug and power management
events, when enabled. These interrupts can either be pin-based or can be MSIs. When
pin-based, the pin that is driven is based on the setting of the D23/24/25/26IP and
D23/24/25/26IR registers. Table 125 summarizes interrupt behavior for Message
Signal Interrupt (MSI) and wire-modes. In the table, “bits” refers to the hot plug and
PME interrupt bits.
8.1.2 Power Management
8.1.2.1 Sleep State Support
Software initiates the transition to S3/S4/S5 by performing a write to PM1C.SLPEN.
After the write completion has been returned to the CPU, each root port will send a
PME_Turn_Off message on its link. The device attached to the link eventually responds
with a PME_TO_Ack followed by a PM_Enter_L23 DLLP to enter L23. When all ports
links are in the L2/3 state, the power management control logic will proceed with the
entry into S3/S4/S5.
8.1.2.2 Resuming from Suspended State
The root port can detect a wake event through the WAKE_B signal and wake the
system. When the root port detects WAKE_B assertion, an internal signal is sent to the
processor power management controller to cause the system to wake up. This internal
message is not logged in any register, nor is an interrupt/GPE generated.
8.1.2.3 Device Initiated PM_PME Message
When the system has returned to S0, a device requesting service sends PM_PME
messages until acknowledged by the processor. If RSTS.PS is cleared, the root port sets
RSTS.PS, and logs the PME Requester ID into RSTS.RID. If RSTS.PS is set, the root port
sets RSTS.PP and logs the PME Requester ID in a hidden register. When RSTS.PS is
cleared, the root port sets RSTS.PS, clears RSTS.PP, and moves the requester ID from
the hidden register into RSTS.RID.
Table 125. MSI vs. PCI IRQ Actions
Interrupt Register Wire-mode Action MSI Action
All bits ‘0’ Wire inactive No action
One or more bits set to ‘1’ Wire active Send message
One or more bits set to ‘1,’ new bit gets set to ‘1’ Wire active Send message
One or more bits set to ‘1,’ software clears some (but not all) bits Wire active Send message
One or more bits set to ‘1,’ software clears all bits Wire inactive No action
Software clears one or more bits, and one or more bits are set on
the same clock.
Wire active Send message