Datasheet
Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
110
7.7.2.22 Offset F4h: LBB - Legacy Backlight Brightness
§ §
03 : 02 01 RW
GFX2X_GFX_R
ATIO
graphics 2x Clock to Graphics Clock Ratio: This field should be set by
software to correspond with the gfx2xclkp (graphics 2x clock) to gfxclkp
(graphics clock) ratio. The field is used to configure the graphics 2D
processing engine.
00: gfx2xclkp to gfxclkp ratio is 1:1
01: gfx2xclkp to gfxclkp ratio is 2:1
10: Reserved
11: Reserved
01 : 00 10 RW GCCR
Graphics Clock to Core Clock Ratio: Set by SW to correspond with the
graphics clock to core clock ratio.
Table 124. Offset F4h: LBB - Legacy Backlight Brightness
Size: 32 bit Default: N/A Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
F4h
F7h
Bit Range Default Access Acronym Description
31 : 24 N/A RW LST3
LBPC Scratch Trigger 3: When written, triggers an interrupt when LBEE
is enabled in Pipe B Status register and the Display B Event is enabled in
IER and unmasked in IMR etc. If written as part of a 16-bit or 32-bit
write, only one interrupt is generated in common.
23 : 16 N/A RW LST2 LBPC Scratch Trigger 2: Same definition as LST3.
15 : 08 N/A RW LST1 LBPC Scratch Trigger 1: Same definition as LST3.
07 : 00 N/A RW LBES
Legacy Backlight Brightness: The value of zero is the lowest
brightness setting and 255 is the brightest. If field LBES is written as part
of a 16-bit (word) or 32-bit (dword) write to LBB, this will cause a flag to
be set (LBES) in the PIPEBSTATUS register and cause an interrupt if
Backlight event in the PIPEBSTATUS register and cause an interrupt if
Backlight Event (LBEE) and Display B Event is enabled by software. (If
field LBES is written as a (one) byte write to LBB (i.e. if only least
significant byte of LBB is written), no flag or interrupt will be generated.)
Table 123. Offset F0h: GCR - Graphics Clock Ratio (Sheet 2 of 2)
Size: 16 bit Default: 0006h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
F0h
F1h
Bit Range Default Access Acronym Description