Datasheet
Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
11
11.7.2.1 Offset 20h: RGEN – Resume Well GPIO Enable............................ 237
11.7.2.2 Offset 24h: RGIO – Resume Well GPIO Input/Output Select.......... 238
11.7.2.3 Offset 28h: RGLVL – Resume Well GPIO Level for Input or Output. 238
11.7.2.4 Offset 2Ch: RGTPE – Resume Well GPIO Trigger Positive Edge
Enable................................................................................... 239
11.7.2.5 Offset 30h: RGTNE – Resume Well GPIO Trigger Negative Edge
Enable................................................................................... 239
11.7.2.6 Offset 34h: RGGPE – Resume Well GPIO GPE Enable ................... 239
11.7.2.7 Offset 38h: RGSMI – Resume Well GPIO SMI Enable.................... 240
11.7.2.8 Offset 3Ch: RGTS – Resume Well GPIO Trigger Status ................. 240
11.7.3 Theory of Operation.............................................................................. 240
11.7.3.1 Power Wells ........................................................................... 240
11.7.3.2 SMI# and SCI Routing............................................................. 240
11.7.3.3 Triggering.............................................................................. 240
11.8 SMBus Controller............................................................................................. 241
11.8.1 Overview ............................................................................................ 241
11.8.2 I/O Registers....................................................................................... 241
11.8.2.1 Offset 00h: HCTL - Host Control Register ................................... 241
11.8.2.2 Offset 01h: HSTS - Host Status Register .................................... 242
11.8.2.3 Offset 02h: HCLK – Host Clock Divider....................................... 243
11.8.2.4 Offset 04h: TSA - Transmit Slave Address.................................. 243
11.8.2.5 Offset 05h: HCMD - Host Command Register .............................. 243
11.8.2.6 Offset 06h: HD0 - Host Data 0.................................................. 244
11.8.2.7 Offset 07h: HD1 - Host Data 1.................................................. 244
11.8.2.8 Offset 20h – 3Fh: HBD – Host Block Data................................... 244
11.8.3 Overview ............................................................................................ 244
11.8.4 Bus Arbitration..................................................................................... 245
11.8.5 Bus Timings......................................................................................... 245
11.8.5.1 Clock Stretching ..................................................................... 245
11.8.5.2 Bus Time Out ......................................................................... 246
11.8.6 SMI#.................................................................................................. 246
11.9 Serial Peripheral Interface ................................................................................ 246
11.9.1 Overview ............................................................................................ 246
11.9.2 Features ............................................................................................. 246
11.9.3 External Interface ................................................................................ 246
11.9.4 SPI Protocol......................................................................................... 247
11.9.4.1 SPI Pin Level Protocol.............................................................. 247
11.9.5 Host Side Interface............................................................................... 249
11.9.5.1 SPI Host Interface Registers..................................................... 249
11.9.5.2 Offset 00h: SPIS – SPI Status .................................................. 250
11.9.5.3 Offset 02h: SPIC – SPI Control ................................................. 251
11.9.5.4 Offset 04h: SPIA – SPI Address ................................................ 252
11.9.5.5 Offset 08h: SPID0 – SPI Data 0 ................................................ 252
11.9.5.6 Offset 10h, 18h, 20h, 28h, 30h, 38h, 40h: SPID[0-6] – SPI Data N253
11.9.5.7 Offset 50h: BBAR – BIOS Base Address ..................................... 253
11.9.5.8 Offset 54h: PREOP – Prefix Opcode Configuration........................ 253
11.9.5.9 Offset 56h: OPTYPE – Opcode Type Configuration ....................... 254
11.9.5.10Offset 58h: OPMENU – Opcode Menu Configuration ..................... 254
11.9.5.11Offset 60h: PBR0 – Protected BIOS Range [0-2] ......................... 255
11.9.5.12Running SPI Cycles from the Host............................................. 256
11.9.5.13Generic Programmed Commands .............................................. 258
11.9.5.14Flash Protection...................................................................... 258
11.9.6 SPI Clocking........................................................................................ 260
11.9.7 BIOS Programming Considerations ......................................................... 260
11.9.7.1 Run Time Updates................................................................... 261
11.9.7.2 BIOS Sector Updates............................................................... 261
11.9.7.3 SPI Initialization ..................................................................... 262
11.10 Watchdog Timer.............................................................................................. 263