Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
109
7.7.2.19 Offset E0h: SWSCISMI - Software SCI/SMI
7.7.2.20 Offset E4h: ASLE - System Display Event Register
7.7.2.21 Offset F0h: GCR - Graphics Clock Ratio
00 0h RW D
Disable: When set, the function is disabled (configuration space is
disabled).
Table 121. Offset E0h: SWSCISMI - Software SCI/SMI
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
E0h
E1h
Bit Range Default Access Acronym Description
15 0 RWO MCS
SCI or SC Event Select: When set, SCI is selected. When cleared, SMI
is selected.
14 : 01 0h RW SS Software Scratch Bits: Used by software. No hardware functionality.
00 0h RW SWSCI Software SCI Event: If MCS is set, setting this bit causes an SCI.
Table 122. Offset E4h: ASLE - System Display Event Register
Size: 32 bit Default: N/A Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
E4h
E7h
Bit Range Default Access Acronym Description
31 : 24 N/A RW AST3
ASLE Scratch Trigger 3: When written, this scratch byte triggers an
interrupt when IER bit 0 is enabled and IMR bit 0 is unmasked. If written
as part of a 16-bit or 32-bit write, only one interrupt is generated in
common.
23 : 16 N/A RW AST2 ASLE Scratch Trigger 2: Same definition as AST3.
15 : 08 N/A RW AST1 ASLE Scratch Trigger 1: Same definition as AST3.
07 : 00 N/A RW AST0 ASLE Scratch Trigger 0: Same definition as AST3.
Table 123. Offset F0h: GCR - Graphics Clock Ratio (Sheet 1 of 2)
Size: 16 bit Default: 0006h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
F0h
F1h
Bit Range Default Access Acronym Description
15 : 04 0 RO RSVD Reserved
Table 120. Offset C4h: FD - Functional Disable (Sheet 2 of 2)
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
C4h
C7h
Bit Range Default Access Acronym Description