Datasheet
Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
108
7.7.2.16 Offset 94h: MA - Message Address
7.7.2.17 Offset 98h: MD - Message Data
7.7.2.18 Offset C4h: FD - Functional Disable
00 0 RW MSIE
MSI Enable: If set, MSI is enabled and traditional interrupts are not
used to generate interrupts. CMD.BME must be set for an MSI to be
generated.
Note: Overall, a MSI interrupt is sent when the expression (IS & ~ID &
BME & MSIE) changes from 0 to 1. Overall, a Message bus interrupt
assert is sent when the expression (IS & ~ID & ~MSIE) changes from 0
to 1. The corresponding Message bus interrupt de-assert is sent when the
expression (IS & ~ID & ~MSIE) changes from 1 to 0. See IS description
for conditions that cause IS bit to be set to 1 and cleared to 0.
Table 118. Offset 94h: MA - Message Address
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
94h
97h
Bit Range Default Access Acronym Description
31 : 02 0 RW ADDR
Address: Lower 32-bits of the system specified message address,
always DW aligned.
01 : 00 0h RO RSVD Reserved.
Table 119. Offset 98h: MD - Message Data
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
98h
99h
Bit Range Default Access Acronym Description
15 : 00 0 RW DATA
Data: This 16-bit field is programmed by system software and is driven
onto the lower word of data during the data phase of the MSI write
transaction
Table 120. Offset C4h: FD - Functional Disable (Sheet 1 of 2)
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
C4h
C7h
Bit Range Default Access Acronym Description
31 : 02 0 RO RSVD Reserved
01 0h RW MD
MSI Disable: When set, the MSI capability pointer is not available - the
item which points to the MSI capability (the power management
capability), will instead indicate that this is the last item in the list.
Table 117. Offset 92h: MC - Message Control (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
92h
93h
Bit Range Default Access Acronym Description