Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
107
7.7.2.12 Offset 58h: SSRW - Software Scratch Read Write
7.7.2.13 Offset 60h: HSRW - Hardware Scratch Read Write
7.7.2.14 Offset 90h: MID - Message Signaled Interrupts Capability
7.7.2.15 Offset 92h: MC - Message Control
Table 114. Offset 58h: SSRW - Software Scratch Read Write
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
58h
5Bh
Bit Range Default Access Acronym Description
31 : 00 00h RO S Scratch: Scratchpad bits.
Table 115. Offset 60h: HSRW - Hardware Scratch Read Write
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
60h
61h
Bit Range Default Access Acronym Description
15 : 00 00h RW RSVD Reserved
Table 116. Offset 90h: MID - Message Signaled Interrupts Capability
Size: 16 bit Default: 0005h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
90h
91h
Bit Range Default Access Acronym Description
15 : 08 00 RO NEXT Pointer to Next Capability: Indicates this is the last item in the list.
07 : 00 05h RO ID Capability ID: Indicates an MSI capability.
Table 117. Offset 92h: MC - Message Control (Sheet 1 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
92h
93h
Bit Range Default Access Acronym Description
15 : 08 00h RO Reserved
07 000h RO C64 64-bit Address Capable: 32-bit capable only.
06 : 04 000h RW MME
Multiple Message Enable: This field is RW for software compatibility,
but only a single message is ever generated.
03 : 01 000 RO MMC Multiple Message Capable: This device is only single message capable.