Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
106
7.7.2.8 Offset 14h: IOBAR - I/O Base Address
This register provides the base offset of 8 bytes of I/O registers within this device.
Access to I/O space is allowed in the D0 state when CMD.IOSE is set. Access is
disallowed in states D1-D3 or if CMD.IOSE is cleared. Access to this space is
independent of VGA functionality.
7.7.2.9 Offset 2Ch: SS - Subsystem Identifiers
This register matches the value written to the LPC bridge.
7.7.2.10 Offset 34h: CAP_PTR - Capabilities Pointer
7.7.2.11 Offset 3Ch: INTR - Interrupt Information
Table 111. Offset 14h: IOBAR - I/O Base Address
Size: 32 bit Default: 00000001h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
14h
17h
Bit Range Default Access Acronym Description
31 : 16 0000h RO RSVD Reserved
15 : 03 0000h RW BA
Base Address: Set by the OS, these bits correspond to address signals
[15:3].
02 : 01 00 RO RSVD Reserved
00 1 RO RTE Resource Type: Indicates a request for I/O space.
Table 112. Offset 34h: CAP_PTR - Capabilities Pointer
Size: 8 bit Default: D0h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
34h
34h
Bit Range Default Access Acronym Description
07 : 00 D0h RO PTR Pointer: The first item in the capabilities list is at address D0h.
Table 113. Offset 3Ch: INTR - Interrupt Information
Size: 16 bit Default: xx00h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
3Ch
3Dh
Bit Range Default Access Acronym Description
15 : 08 Variable RO IPIN
Interrupt Pin: This value reflects the value of D02IP.GP in the LPC
configuration space.
07 : 00 00h RW ILIN
Interrupt Line: Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this
bit.