Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
105
7.7.2.6 Offset 0Eh: HDR - Header Type
7.7.2.7 Offset 10h: MMADR - Memory Mapped Base Address
This register requests allocation for the IGD registers and instruction ports. The
allocation is for 512 KB.
15 : 08
00h/80
h
RO SCC
Sub-Class Code: When GC.VD is cleared, this value is 00h. When GC.VD
is set, this value is 80h.
07 : 00 00h RO PI Programming Interface: Indicates a display controller.
Table 109. Offset 0Eh: HDR - Header Type
Size: 8 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
0Eh
0Eh
Bit Range Default Access Acronym Description
07 0 RO MFUNC Multi Function Status: Integrated graphics is a single function.
06 : 00 00h RO HDR Header Code: Indicates a type 0 header format.
Table 108. Offset 09h: CC - Class Codes (Sheet 2 of 2)
Size: 24 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
09h
0Bh
Bit Range Default Access Acronym Description
Table 110. Offset 10h: MMADR - Memory Mapped Base Address
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
10h
13h
Bit Range Default Access Acronym Description
31 : 19 0000h RW BA
Base Address: Set by the OS, these bits correspond to address signals
[31:19].
18 : 01 0000h RO RSVD Reserved
00 0 RO RTE Resource Type: Indicates a request for memory space.