Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
104
7.7.2.3 Offset 06h: STS - PCI Status
7.7.2.4 Offset 08h: RID - Revision Identification
This value matches the revision ID register of the LPC bridge.
7.7.2.5 Offset 09h: CC - Class Codes
00 0 RW IOSE
I/O Space Enable: When set, accesses to this device’s I/O space is
enabled.
Table 106. Offset 06h: STS - PCI Status
Size: 16 bit Default: 0010h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
06h
07h
Bit Range Default Access Acronym Description
15 : 05 0 RO RSVD Reserved
04 1 RO CAP
Capability List: Indicates that the register at 34h provides an offset into
PCI Configuration Space containing a pointer to the location of the first
item in the list.
03 0 RO IS
Interrupt Status: Reflects the state of the interrupt in the device in the
graphics device.
02 : 00 000b RO RSVD Reserved
Table 105. Offset 04h: CMD – PCI Command (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
04h
05h
Bit Range Default Access Acronym Description
Table 107. Offset 08h: RID - Revision Identification
Size: 8 bit Default: Refer to bit description Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
08h
08h
Bit Range Default Access Acronym Description
7:0
Refer to
bit
descript
ion
RO RID
Revision ID: Refer to the Intel
®
Atom™ Processor E6x5C Series
Specification Update for the value of the Revision ID Register. For the B-0
Stepping, this value is 01h. For B-1 Stepping, this value is 02h.
Table 108. Offset 09h: CC - Class Codes (Sheet 1 of 2)
Size: 24 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
09h
0Bh
Bit Range Default Access Acronym Description
23 : 16
Refer to
bit
descript
ion
RO BCC
Base Class Code: Indicates a display controller.
For B-0 stepping, this value is 03h. For B-1 stepping, this value is 04h.