Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
103
7.7.2.1 Offset 00h: ID – Identifiers
7.7.2.2 Offset 04h: CMD – PCI Command
34 35
CAP_PT
R
Capabilities Pointer
3C 3D INTR Interrupt Information
58 5B SSRW Software Scratch Read Write
60 61 HSRW Hardware Scratch Read Write
90 91 MID Message Signaled Interrupts Capability
92 93 MC Message Control
94 97 MA Message Address
98 99 MD Message Data
C4 C7 FD Functional Disable
E0 E1
SWSCI
SMI
Software SCI/SMI
E4 E7 ASLE System Display Event Register
F0 F1 GCR Graphics Clock Ratio
F4 F7 LBB Legacy Backlight Brightness
Table 104. Offset 00h: ID – Identifiers
Size: 32 bit Default: 81828086h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
00h
03h
Bit Range Default Access Acronym Description
31 : 16 8182h RO DID
Device Identification Number: Identifier assigned to the processor
core/primary PCI device. The lower 3 bits of this register are determined
by a fuse.
15 : 00 8086h RO VID Vendor Identification Number: PCI standard identification for Intel.
Table 105. Offset 04h: CMD – PCI Command (Sheet 1 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:3:0
Offset Start:
Offset End:
04h
05h
Bit Range Default Access Acronym Description
15 : 11 00h RSVD Reserved
10 0 RW ID
Interrupt Disable: This bit disables the device from asserting INTx_B.
When cleared, enables the assertion of this device’s INTx_B signal. When
set, disables the assertion of this device’s INTx_B signal.
09 : 03 0 RSVD Reserved
02 0 RW BME
Bus Master Enable: Enables the IGD to function as a PCI compliant
master.
01 0 RW MSE
Memory Space Enable: When set, accesses to this device’s memory
space is enabled.
Table 103. PCI Header (Sheet 2 of 2)
Start End Symbol Register Name