Datasheet
Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
102
7.7.2 D3:F0 PCI Configuration Registers
23 :16 00h RW SCRATCH_2
Software scratch byte 2. Any write to this byte, even writing back the
same value read, will trigger GVD to send the contents of
LEGACY_BACKLIGHT_BRIGHTNESS byte to the VSunit.
15 :8 00h RW SCRATCH_1
Software scratch byte 1. Any write to this byte, even writing back the
same value read, will trigger GVD to send the contents of
LEGACY_BACKLIGHT_BRIGHTNESS byte to the VSunit.
7 :0 00h RW
LEGACY_BACKL
IGHT_BRIGHTN
ESS
LBES: The value of zero is the lowest brightness setting and the value of
255 is the brightest. A write to this register will cause a flag to be set
(LBES) in the PIPEBSTATUS register and cause an interrupt if Backlight
event in the PIPEBSTATUS register and cause an Interrupt if Backlight
Event (LBEE) and Display B Event is enabled by software. The field value
(byte) is forwarded by the GVD to the Vsunit.
Table 102. FCh: GVD.ASLS ASL – ASL Storage
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
FCh
Message Bus Port:
06h
Register Address: 3Fh
Bit Range Default Access Acronym Description
31 :0
000000
00h
RW SCRATCH
This register provides a means for the BIOS to communicate with the
driver. This definition of this scratch register is worked out in common
between System BIOS and driver software. Storage for up to 6 devices is
possible. For each device, the ASL control method requires two bits for
_DOD (BIOS detectable yes or no, VGA/NonVGA), one bit for _DGS
(enable/disable requested), and two bits for DCS (enabled now/disabled
now, connected or not).
Table 103. PCI Header (Sheet 1 of 2)
Start End Symbol Register Name
00 03 ID Identifiers
04 05 CMD Command
06 07 STS Device Status
08 08 RID Revision Identification
09 0B CC Class Codes
0E 0E HTYPE Header Type
10 13 MMABR Memory Mapped Base Address
14 17 IOBAR I/O Base Address
2C 2F SS Subsystem Identifiers
Table 101. F4h: GVD.LBB – Legacy Backlight Brightness (Sheet 2 of 2)
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
F4h
Message Bus Port:
06h
Register Address: 39h
Bit Range Default Access Acronym Description