Datasheet
Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
100
Table 97. D0h: GVD.PMCAP – Power Management Capabilities
Size: 32 bit Default: 0022B001h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
D0h
Message Bus Port:
06h
Register Address: 34h
Bit Range Default Access Acronym Description
31 :27 00h RO PME_SUPPORT PMES The graphics controller does not generate PME#.
26 0b RO D2_SUPPORT D2S: The D2 power management state is not supported.
25 0b RO D1_SUPPORT D1S: The D1 power management state is not supported.
24 :22 000b RO RESERVED Reserved
21 1b RO
DEVICE_SPECI
FIC_INITIALIZA
TION
Hardwired to 1 to indicate that special initialization of the graphics
controller is required before generic class device driver is to use it.
20 :19 00b RO RESERVED Reserved
18 :16 010b RO VERSION
VS: Indicates compliance with revision 1.1 of the PCI Power Management
Specification.
15 :8 B0h RO NEXT_POINTER Indicates the next item in the capabilities list.
7 :0 01h RO
CAPABILITIES_
ID
CAPID: SIG defines this ID is 01h for power management.
Table 98. D4h: GVD.PMCS – Power Management Control/Status
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
D4h
Message Bus Port:
06h
Register Address: 35h
Bit Range Default Access Acronym Description
31 :2
000000
00h
RO RESERVED Reserved
1:0 00b RW
POWER_STATE
_PS
In the processor, power management is implemented by writing to
control registers in the Punit. This field may be programmed by the
software driver, but no action is taken based on writing to this field.
Table 99. E0h: GVD.SWSMISCI – Software SMI or SCI (Sheet 1 of 2)
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
E0h
Message Bus Port:
06h
Register Address: 38h
Bit Range Default Access Acronym Description
31 :16 0000h RO RESERVED Reserved
15 0b RW
SMI_OR_SCI_E
VENT_SELECT
MCS: SMI or SCI event select. 0 = SMI 1 = SCI
14 :1 0000h RW
SOFTWARE_SC
RATCH_BITS
Used by driver to communicate information to SBIOS. No hardware
functionality.