Datasheet
Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
10
11.3.6.3 Automatic Rotation Mode (Equal Priority Devices) ........................221
11.3.6.4 Specific Rotation Mode (Specific Priority)....................................221
11.3.6.5 Poll Mode ...............................................................................221
11.3.6.6 Edge and Level Triggered Mode.................................................222
11.3.7 End Of Interrupt (EOI) ..........................................................................222
11.3.7.1 Normal EOI ............................................................................222
11.3.7.2 Automatic EOI ........................................................................222
11.3.8 Masking Interrupts................................................................................222
11.3.8.1 Masking on an Individual Interrupt Request ................................222
11.3.8.2 Special Mask Mode ..................................................................222
11.3.9 Steering of PCI Interrupts......................................................................223
11.4 Advanced Peripheral Interrupt Controller (APIC) ..................................................223
11.4.1 Memory Registers.................................................................................223
11.4.1.1 Address FEC00000h: IDX – Index Register .................................223
11.4.1.2 Address FEC00010h: WDW – Window Register ............................223
11.4.1.3 Address FEC00040h: EOI – EOI Register ....................................223
11.4.2 Index Registers ....................................................................................224
11.4.2.1 Offset 00h: ID – Identification Register ......................................224
11.4.2.2 Offset 01h: VS – Version Register..............................................224
11.4.2.3 Offset 10-11h – 3E-3Fh: RTE[0-23] – Redirection Table Entry .......225
11.4.3 Unsupported Modes ..............................................................................226
11.4.4 Interrupt Delivery.................................................................................226
11.4.4.1 Theory of Operation.................................................................226
11.4.4.2 EOI .......................................................................................226
11.4.4.3 Interrupt Message Format ........................................................226
11.4.4.4 Interrupt Delivery Address Value...............................................226
11.4.4.5 Interrupt Delivery Data Value ...................................................227
11.4.5 PCI Express* Interrupts.........................................................................227
11.4.6 Routing of Internal Device Interrupts.......................................................227
11.5 Serial Interrupt ...............................................................................................227
11.5.1 Overview.............................................................................................227
11.5.2 Start Frame .........................................................................................228
11.5.3 Data Frames ........................................................................................228
11.5.4 Stop Frame..........................................................................................228
11.5.5 Serial Interrupts Not Supported..............................................................229
11.5.6 Data Frame Format and Issues...............................................................229
11.6 Real Time Clock...............................................................................................230
11.6.1 Overview.............................................................................................230
11.6.2 I/O Registers .......................................................................................230
11.6.3 Indexed Registers.................................................................................230
11.6.3.1 Offset 0Ah: Register A .............................................................231
11.6.3.2 Offset 0Bh: Register B - General Configuration............................232
11.6.3.3 Offset 0Ch: Register C - Flag Register (RTC Well) ........................232
11.6.3.4 Offset 0Dh: Register D - Flag Register (RTC Well)........................233
11.6.4 Update Cycles ......................................................................................233
11.6.5 Interrupts............................................................................................233
11.7 General Purpose I/O.........................................................................................234
11.7.1 Core Well GPIO I/O Registers .................................................................234
11.7.1.1 Offset 00h: CGEN – Core Well GPIO Enable.................................234
11.7.1.2 Offset 04h: CGIO – Core Well GPIO Input/Output Select...............235
11.7.1.3 Offset 08h: CGLVL – Core Well GPIO Level for Input or Output ......235
11.7.1.4 Offset 0Ch: CGTPE – Core Well GPIO Trigger Positive Edge Enable.235
11.7.1.5 Offset 10h: CGTNE – Core Well GPIO Trigger Negative Edge Enable236
11.7.1.6 Offset 14h: CGGPE – Core Well GPIO GPE Enable ........................236
11.7.1.7 Offset 18h: CGSMI – Core Well GPIO SMI Enable.........................236
11.7.1.8 Offset 1Ch: CGTS – Core Well GPIO Trigger Status ......................237
11.7.2 Resume Well GPIO I/O Registers.............................................................237