Intel® Atom™ Processor E6xx Series Datasheet April 2013 Revision 005US Document Number: 324208-005US
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Contents Contents 1.0 Introduction ............................................................................................................ 23 1.1 Terminology ..................................................................................................... 24 1.2 Reference Documents ........................................................................................ 25 1.3 Components Overview ....................................................................................... 26 1.3.
Contents 3.8 3.9 3.10 3.11 3.12 3.13 3.14 SPI Interface Signals..........................................................................................48 Power Management Interface Signals ...................................................................48 Real Time Clock Interface Signals ........................................................................49 JTAG and Debug Interface ..................................................................................
Contents 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 DRAM Partial Writes........................................................................................... 69 DRAM Power Management .................................................................................. 69 6.4.1 Powerdown Modes .................................................................................. 70 6.4.2 Self Refresh Mode .................................................................................. 70 6.4.
Contents 7.7.2.8 7.7.2.9 7.7.2.10 7.7.2.11 7.7.2.12 7.7.2.13 7.7.2.14 7.7.2.15 7.7.2.16 7.7.2.17 7.7.2.18 7.7.2.19 7.7.2.20 7.7.2.21 7.7.2.22 8.0 Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset 14h: IOBAR - I/O Base Address ....................................... 106 2Ch: SS - Subsystem Identifiers ...................................... 106 34h: CAP_PTR - Capabilities Pointer.................................. 106 3Ch: INTR - Interrupt Information..
Contents 8.2.3 8.2.4 8.2.5 8.2.6 9.0 8.2.2.9 SLCAP — Slot Capabilities ........................................................ 127 8.2.2.10 SLCTL — Slot Control .............................................................. 127 8.2.2.11 SLSTS — Slot Status ............................................................... 128 8.2.2.12 RCTL — Root Control ............................................................... 129 8.2.2.13 RCAP — Root Capabilities.....................................................
Contents 9.3.1.28 9.3.1.29 9.3.1.30 9.3.1.31 9.3.1.32 9.3.1.33 9.3.1.34 9.3.1.35 9.3.1.36 9.3.1.37 9.3.1.38 9.3.1.39 9.3.1.40 9.3.1.41 9.3.1.42 9.3.1.43 9.3.1.44 9.3.2 Offset 72h: PCIECAP – PCI Express* Capabilities Register ............. 151 Offset 74h: DEVCAP – Device Capabilities Register....................... 151 Offset 78h: DEVC – Device Control ............................................ 151 Offset 7Ah: DEVS – Device Status Register .................................
Contents 11.0 ACPI Devices ......................................................................................................... 201 11.1 8254 Timer .................................................................................................... 201 11.1.1 Counter 0, System Timer ...................................................................... 201 11.1.2 Counter 1, Refresh Request Signal.......................................................... 201 11.1.3 Counter 2, Speaker Tone..............
Contents 11.4 11.5 11.6 11.7 11.3.6.3 Automatic Rotation Mode (Equal Priority Devices) ........................ 221 11.3.6.4 Specific Rotation Mode (Specific Priority) .................................... 221 11.3.6.5 Poll Mode ............................................................................... 221 11.3.6.6 Edge and Level Triggered Mode ................................................. 222 11.3.7 End Of Interrupt (EOI) ........................................................................
Contents 11.7.2.1 11.7.2.2 11.7.2.3 11.7.2.4 Offset 20h: RGEN – Resume Well GPIO Enable............................ 237 Offset 24h: RGIO – Resume Well GPIO Input/Output Select.......... 238 Offset 28h: RGLVL – Resume Well GPIO Level for Input or Output . 238 Offset 2Ch: RGTPE – Resume Well GPIO Trigger Positive Edge Enable................................................................................... 239 11.7.2.5 Offset 30h: RGTNE – Resume Well GPIO Trigger Negative Edge Enable........................
Contents 11.10.1Overview ............................................................................................. 263 11.10.2Features .............................................................................................. 263 11.10.3Watchdog Timer Register Details ............................................................ 263 11.10.3.1Offset 00h: PV1R0 - Preload Value 1 Register 0 ........................... 264 11.10.3.2Offset 01h: PV1R1 - Preload Value 1 Register 1 .........................
Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 PCI Devices and Functions......................................................................................... 26 Intel® Atom™ Processor E6xx Series SKU for Different Segments................................... 30 Buffer Types............................................................................................................
Contents 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 312Ch: D23IP – Device 23 Interrupt Pin ......................................................................63 3130h: D03IP – Device 3 Interrupt Pin ........................................................................64 Interrupt Route Configuration ........................................................................
Contents 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 Offset 0Eh: HDR - Header Type................................................................................ 105 Offset 10h: MMADR - Memory Mapped Base Address .................................................. 105 Offset 14h: IOBAR - I/O Base Address ............................
Contents 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 PCI Bridge Vendor Capability.................................................................................... 130 Offset 90h: SVCAP — Subsystem Vendor Capability .................................................... 130 Offset 94h: SVID — Subsystem Vendor IDs ...................
Contents 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 120h: VC1CTL – VC1 Resource Control Register ......................................................... 155 126h: VC1STS – VC1 Resource Status Register .......................................................... 156 130h: RCCAP – Root Complex Link Declaration Enhanced Capability Header Register ......
Contents 266 98h, B8h, D8h, F8h: ISD0BDPL, ISD1BDPL, OSD0BDPL, OSD1BDPL – Input/Output Stream Descriptor [0-1] Buffer Descriptor List Pointer Register ..................................... 181 267 1000h: EM1 – Extended Mode 1 Register ................................................................... 182 268 1004h: INRC – Input Stream Repeat Count Register ................................................... 183 269 1008h: OUTRC – Output Stream Repeat Count Register.........................................
Contents 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 21h, A1h: ICW4 – Initialization Command Word 4 Register .......................................... 215 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt Mask) .................................. 216 20h, A0h: OCW2 – Operational Control Word 2 ..................................
Contents 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 00h: SPIS - SPI Status............................................................................................ 250 02h: SPIC - SPI Control........................................................................................... 251 04h: SPIA - SPI Address..........................................................................................
Revision History Revision History Date April 2013 July 2011 January 2011 Revision Description 005 Updated Section 5.2, “Introduction” on page 53 Updated Table 96, “C4h: GVD.FD – Functional Disable” on page 99 Updated Table 104, “Offset 00h: ID – Identifiers” on page 103 Updated Section 11.10.1, “Overview” on page 263 Updated Section 11.10.4.
Revision History Date Revision Description October 2010 002 Updated Table 2, “Intel® Atom™ Processor E6xx Series SKU for Different Segments” on page 30 Updated Table 15. Added an additional step in WDT mode — users need to program the preload value 1 register to all 0’s. Added Overshoot/Undershoot specs Updated Table 34, “Intel® Atom™ Processor E6xx Series Clock Domains” on page 57 Updated Section 5.3, “System Memory Map” on page 60 Corrected PCI-E port number Section 8.
Introduction 1.0 Introduction The Intel® Atom™ Processor E6xx Series is the next-generation Intel® architecture (IA) CPU for the small form factor ultra low power embedded segments based on a new architecture partitioning. The new architecture partitioning integrates the 3D graphics engine, memory controller and other blocks with the IA CPU core. Please refer to subsequent chapters for a detailed description of functionality.
Introduction 1.1 Terminology Term Description ACPI Advanced Configuration and Power Interface ADD2 Advanced Digital Display 2. An interface specification that accepts serial DVO inputs and translates them into different display outputs such as DVO, TVOUT, and LVDS.
Introduction Term SCI System Control Interrupt. SCI is used in the ACPI protocol. SDRAM Synchronous Dynamic Random Access Memory SDVO Serial Digital Video Out. SDVO is a digital display channel that serially transmits digital display data to an external SDVO device. The SDVO device accepts this serialized format and then translates the data into the appropriate display format (i.e., TMDS, LVDS, TV-Out).
Introduction 1.3 Components Overview The Intel® Atom™ Processor E6xx Series incorporates a variety of PCI functions as listed in Table 1. Table 1.
Introduction 1.3.1 Low-Power Intel® Architecture Core • 600 MHz (Ultra Low Power SKU), 1.0 GHz (Entry SKU), 1.3 GHz (Mainstream SKU) and 1.
Introduction 1.3.4 Video Decode The Intel® Atom™ Processor E6xx Series supports MPEG2, MPEG4, VC1, WMV9, H.264 (main, baseline at L3 and high-profile level 4.0/4.1), and DivX*. 1.3.5 Video Encode The Intel® Atom™ Processor E6xx Series supports MPEG4, H.264 (baseline at L3), and VGA. 1.3.6 Display Interfaces The Intel® Atom™ Processor E6xx Series supports LVDS and Serial DVO display ports permitting simultaneous independent operation of two displays. 1.3.6.
Introduction 1.3.9 Intel® High Definition Audioβ (Intel® HD Audioβ) Controller The Intel® High Definition Audioβ Specification defines a digital interface that can be used to attach different types of codecs (such as audio and modem codecs). The Intel® HD Audioβ controller supports up to four audio streams, two in and two out.
Introduction 1.3.14 Watchdog Timer (WDT) The Intel® Atom™ Processor E6xx Series supports a user configurable watchdog timer. It contains selectable prescaler approximately 1 µs to 10 min. When the WDT triggers, GPIO[4] is asserted. 1.3.15 Real Time Clock (RTC) The Intel® Atom™ Processor E6xx Series supports a RTC that provides a battery backed-up date and time keeping device. The time keeping comes from a 32.768 kHz oscillating source. 1.3.
Signal Description 2.0 Signal Description This chapter provides a detailed description of the signals and boot strap definitions. The processor signals are arranged in functional groups according to their associated interface. Each signal description table has the following headings: • Signal: The name of the signal/pin • Type: The buffer direction and type. Buffer direction can be either input, output, or I/O (bidirectional). See Table 3 for definitions of the different buffer types.
Signal Description 2.1 System Memory Signals Table 4. System Memory Signals Signal Direction/Type Power Well Description M_ODT[1:0] O CMOS1.8 Core On-Die Termination Enable: (active high) One pin per rank (2 ranks supported) M_CKP O CMOS1.8 Core Differential DDR Clock: The crossing of the positive edge of M_CKP and the negative edge of M_CKN is used to sample the address and control signals on memory. M_CKN O CMOS1.8 Core Complementary Differential DDR Clock M_CKE[1:0] O CMOS1.
Signal Description 2.2 Integrated Display Interfaces 2.2.1 LVDS Signals Table 5. LVDS Signals Signal Direction/Type Power Well Description LVD_DATAN_0 O LVDS Core Channel A Differential Data Output (Negative): Differential signal pair. LVD_DATAN_1 O LVDS Core Channel A Differential Data Output (Negative): Differential signal pair. LVD_DATAN_2 O LVDS Core Channel A Differential Data Output (Negative): Differential signal pair.
Signal Description 2.2.2 Serial Digital Video Output (SDVO) Signals Table 6. Serial Digital Video Output Signals Signal Name SDVO_REDP SDVO_REDN SDVO_GREENP SDVO_GREENN SDVO_BLUEP SDVO_BLUEN Direction/Type O PCIe* O PCIe* O PCIe* SDVO_CLKP SDVO_CLKN O PCIe* SDVO_INTP SDVO_INTN I PCIe* Power Well Description Core Serial Digital Video Red: SDVO_RED[±] is a differential data pair that provides red pixel data for the SDVO channel during Active periods.
Signal Description 2.3 PCI Express* Signals Table 7. PCI Express* Signals Direction/Type Power Well PCIE_PETp[3:0] PCIE_PETn[3:0] O PCIe* Core PCI Express* Transmit: PCIE_PET[3:0] are PCI Express* Ports 3:0 transmit pair (P and N) signals. PCIE_PERp[3:0] PCIE_PERn[3:0] I PCIe* Core PCI Express* Receive: PCIE_PER[3:0] PCI Express* Ports 3:0receive pair (P and N) signals. PCIE_CLKINP PCIE_CLKINN I PCIe* Core PCI Express* Input Clock: 100-MHz differential clock signals.
Signal Description 2.5 LPC Interface Signals Table 9. LPC Interface Signals Direction/ Type Power Well LPC_AD[3:0] I/O CMOS3.3 Core LPC Address/Data: Multiplexed Command, Address, Data LPC_FRAME_B O CMOS3.3 Core LPC Frame: This signal indicates the start of an LPC cycle. LPC_SERIRQ I/O CMOS3.3 Core Serial Interrupt Request: This signal conveys the serial interrupt protocol. LPC_CLKRUN_B I/O CMOS3.3 Core Clock Run: This signal gates the operation of the LPC_CLKOUTx.
Signal Description 2.8 Power Management Interface Signals Table 12. Power Management Interface Signals Direction/ Type Power Well Description RESET_B I CMOS3.3 SUS System Reset: Active Low Hard Reset for the processor. When asserted, the processor will immediately initialize itself and return to its default state. This signal is driven by the Power Management IC. PWROK I CMOS3.3 RTC Power OK: When asserted, PWROK is an indication to the system that core power is stable.
Signal Description 2.9 Real Time Clock Interface Signals Table 13. Real Time Clock Interface Signals Direction/ Type Power Well Description RTCX1 Special A RTC Crystal Input 1: This signal is connected to the 32.768-kHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. RTCX2 Special A RTC Crystal Output 2: This signal is connected to the 32.768kHz crystal. If no external crystal is used, then RTCX2 should be left floating.
Signal Description 2.11 Miscellaneous Signals and Clocks Table 15. Miscellaneous Signals and Clocks (Sheet 1 of 4) Signal Name Direction/ Type Power Well Description Legacy (North Complex) CMREF I Power Core Non-Strobe Signals’ Reference Voltage for DMI: Externally set via passive voltage divider. 1 KΩ to Vccp. 1 KΩ to Vss. GTLREF I Power Core Strobe Signals’ Reference Voltage for DMI: Externally set via passive voltage divider. 1 KΩ to Vccp. 1 KΩ to Vss.
Signal Description Table 15. Miscellaneous Signals and Clocks (Sheet 2 of 4) Signal Name GPIO_B THERMTRIP_B Direction/ Type Power Well Description Core General Purpose I/O / External Thermal Sensor: Same pin type as BPM[]. GPIO in this case is NOT the ACPI notion with lots of software configurability. Instead, this is essentially a spare pin that can be configured as a input or output which the microcontroller can respond to. It can also be configured as an external thermal sensor input.
Signal Description Table 15. Miscellaneous Signals and Clocks (Sheet 3 of 4) Signal Name Direction/ Type Power Well Description O CMOS Core Voltage ID Enable: Indicates which voltage is being specified on the VID pins: 00: VID is Invalid 01: VID = Vcc 10: VID = Vnn 11: Unused TEST_B I CMOS3.3 SUS TEST: When asserted, component is put into TEST modes combinatorially. RCOMP I A Core Connect 249 Ω resistor to 1.
Signal Description Table 15. Miscellaneous Signals and Clocks (Sheet 4 of 4) Signal Name THRM_B Direction/ Type Power Well I CMOS3.3 Core Description Thermal Alarm: Generated by external hardware to generate SMI_B/SCI. CRU/PLL HPLL_REFCLK_P HPLL_REFCLK_N I CMOS Core 2.12 General Purpose I/O Table 16. General Purpose I/O Signals Signal Name 2.13 Type Reference clock: Host PLL CLK Differential pair: 100 MHz. Power Well Description GPIO_SUS[8:0] I/O CMOS3.
Signal Description Table 17. Functional Straps (Sheet 2 of 2) Signal Name 2.14 Strap Definition GPIO[0] STRAP_BOOT_FLASH: Defines whether TC boots from SPI or LPC 1: SPI 0: LPC Notes: Boot from LPC is not supported. GPIO[3:2] STRAP_CMC_BA[1:0] = GPIO[3:2]. CMC Base Address, defined the address the CMC will start fetching and executing code from 10 = 0xFFFE0000 11 = 0xFFFD0000 01 = 0xFFFC0000 00 = 0xFFFB0000 GPIO[4] STRAP_LPCCLK_STRENGTH: LPC_CLKOUT[0] Buffer Strength Control.
Signal Description Table 18. Power and Ground Signals (Sheet 2 of 2) Signal Name Nominal Voltage Description VCCD_DPL 1.05 V DPLL dedicated supply VCCA_PEG 1.05 V Used by PCIe* and SDVO VCCSFR_EXP 1.8 V PCIe* superfilter regulator VCCSFRDPLL 1.8 V SDVO superfilter regulator VCCSFRHPLL 1.8 V HPLL superfilter regulator VCCQHPLL 1.05 V HPLL quiet supply VCCFHV 1.05 V Can be connected to VCCP VMM 1.05 V Connect to 1.05 V VSS 0V Ground pin.
Pin States 3.0 Pin States This chapter describes the states of each Intel® Atom™ Processor E6xx Series signal in and around reset. It also documents what signals have internal pull-up/pulldown/series termination resistors and their values. 3.1 Pin Reset States Table 19. Reset State Definitions Buffer Type Buffer Description High-Z The processor places this output in a high-impedance state.
Pin States Table 20. System Memory Signals (Sheet 2 of 2) Signal Name M_DM[3:0] Direction Reset Post-Reset S3 S4/S5 O High-Z High-Z High-Z High-Z VIXunknown M_RCVENIN I VIX-unknown VIX-unknown VIXunknown M_RCVENOUT O High-Z VOL High-Z High-Z VIX-unknown VIXunknown VIXunknown M_RCOMPOUT I VIX-unknown 3.3 Integrated Display Interfaces 3.3.1 LVDS Signals Table 21.
Pin States Table 22.
Pin States 3.6 LPC Interface Signals Table 25. LPC Interface Signals Signal Name LPC_AD[3:0] LPC_FRAME_B Direction Reset Post-Reset S3 S4/S5 I/O High-Z High-Z Off Off O VOH VOH Off Off LPC_SERIRQ I/O High-Z High-Z Off Off LPC_CLKRUN_B I/O VOL VOL Off Off O VOH VOH Off Off LPC_CLKOUT[2:0] 3.7 SMBus Interface Signals Table 26.
Pin States Table 28. Power Management Interface Signals (Sheet 2 of 2) Signal Name Direction Reset Post-Reset S3 SLPRDY_B O VOH VOH VOH Off RSTRDY_B O VOH VOH VOH Off GPE_B I VIX-unknown VIX-unknown VIX-unknown Off 3.10 Real Time Clock Interface Signals Table 29. Real Time Clock Interface Signals Signal Name 3.
Pin States 3.13 General Purpose I/O Table 32. General Purpose I/O Signals Signal Name Direction Reset Post-Reset S3 S4/S5 GPIOSUS[8:0] I/O High-Z High-Z Unknown Off GPIO[4:0] I/O High-Z High-Z Off Off 3.14 Integrated Termination Resistors Table 33.
System Clock Domains 4.0 System Clock Domains The Intel® Atom™ Processor E6xx Series contains many clock frequency domains to support its various interfaces. Table 34 summarizes these domains. Table 34. Intel® Atom™ Processor E6xx Series Clock Domains Clock Domain Signal Name Frequency Source Usage Processor BCLKP/BCLKN 100 MHz Main clock generator Processor reference clock Processor HPLL_REFCLK_P HPLL_REFCLK_N 100 MHz Main clock generator Processor reference clock CLK14 CLK14 14.
System Clock Domains Intel® Atom™ Processor E6xx Series Datasheet 52
Register and Memory Mapping 5.0 Register and Memory Mapping This chapter describes the I/O and memory map settings for the Intel® Atom™ Processor E6xx Series in the MCP. 5.1 Address Map The Intel® Atom™ Processor E6xx Series contains registers that are located in the processor’s memory and I/O space. It also contains sets of PCI configuration registers that are located in a separate configuration space. Table 35.
Register and Memory Mapping • Control registers are I/O mapped into the processor I/O space that controls access to PCI and PCI Express* configuration space. • Internal configuration registers residing within the processor are partitioned into nine logical device register sets, one for each PCI device listed in Table 39. (These are “logical” devices because they reside within a single physical device.
Register and Memory Mapping Figure 3. System Address Map 4GB PCI Memory Address Range Top of Memory 2GB Main Memory Address Range 1 MB Legacy Address Range 0 Table 36.
Register and Memory Mapping Table 36. Memory Map (Sheet 2 of 2) Device Start Address High BIOS FFC00000 End Address Comments The Chipset Microcode (CMC) base address lives within the LPC space and consumes 64 kB of space. Make sure to avoid using the same starting address for other LPC devices in the system.
Register and Memory Mapping Table 37. Fixed I/O Range Decoded by the Processor (Sheet 2 of 2) I/O Address 5.3.1.
Register and Memory Mapping Table 39. PCI Devices and Functions (Sheet 2 of 2) Bus: Device: Function # Figure 4. Functional Description Bus 0: Device 25: Function 0 PCI Express* Port 2 Bus 0: Device 26: Function 0 PCI Express* Port 3 Bus 0: Device 27: Function 0 Intel® High Definition Audioβ Controller Bus 0: Device 31: Function 0 LPC Interface PCI Devices Intel® Atom™ Processor E6xx Series PCI-E2 PCI-E3 IOH 5.
Register and Memory Mapping 5.4.1.2 IO BAR The Intel® Atom™ Processor E6xx Series uses a programmable base address (BAR) to set a range of IO locations that it will use to decode PORT IN and/or PORT OUT from the CPU and directly accesses a register(s). The BAR register is generally located in the PCI configuration space and is programmable by the BIOS/OS. 5.4.1.
Register and Memory Mapping Table 41. PCI Configuration Memory Bar Mapping Field 5.5 Configuration Cycle Bits Memory Cycle Bits Bus Number 31:24 27:20 Device Number 23:19 19:15 Function Number 18:16 14:12 Register Number 11:02 11:02 Bridging and Configuration This describes all registers and base functionality that is related to chipset configuration and not a specific interface. It contains the root complex register block. This block is mapped into memory space, using RCBA.
Register and Memory Mapping 5.5.1.2 Offset 0004h: ESD – Element Self Description Table 44. 0004h: ESD – Element Self Description Size: 32 bit Default: Memory Mapped IO Bit Range Default Power Well: BAR: RCBA Access Acronym Offset: 0004h - 0007h Description 31 :24 00h RO PN Port Number: A value of 0 indicates the egress port. 23 :16 00h RWO CID Component ID: This indicates the component ID assigned to this element by software.
Register and Memory Mapping 5.5.2 Interrupt Pin Configuration The following registers tell each device which interrupt pint to report in the IPIN register of their configuration space, as shown in Table 47. Table 47. Interrupt Pin Configuration Bits Pin Bits Pin 0h No Interrupt 1h INTA_B 2h INTB_B 3h INTC_B 4h INTD_B 5h-Fh Reserved 5.5.2.1 Offset 3100h: D31IP – Device 31 Interrupt Pin Table 48.
Register and Memory Mapping 5.5.2.4 Offset 3120h: D26IP – Device 26 Interrupt Pin Table 51. 3120h: D26IP – Device 26 Interrupt Pin Size: 32 bit Default: Memory Mapped IO Bit Range Default Power Well: BAR: RCBA Access Acronym Offset: 3120h Description 31 :04 0 RO RSVD Reserved 03 :00 1h RW P4IP PCI Express* #4 Pin: Indicates which pin PCI Express* port #3 uses 5.5.2.5 Offset 3124h: D25IP – Device 25 Interrupt Pin Table 52.
Register and Memory Mapping 5.5.2.8 Offset 3130h: D03IP – Device 3 Interrupt Pin Table 55. 3130h: D03IP – Device 3 Interrupt Pin Size: 32 bit Default: Memory Mapped IO Bit Range Default 31 :04 03 :00 0 1h 5.5.
Register and Memory Mapping 5.5.3.2 Offset 3148h: D27IR – Device 27 Interrupt Route Table 58.
Register and Memory Mapping 5.5.3.5 Offset 314Eh: D24IR – Device 24 Interrupt Route Table 61.
Register and Memory Mapping 5.5.3.8 Offset 3162h: D03IR – Device 3 Interrupt Route Table 64.
Register and Memory Mapping Intel® Atom™ Processor E6xx Series Datasheet 68
Memory Controller 6.0 Memory Controller 6.1 Overview The Intel® Atom™ Processor E6xx Series contains an integrated 32-bit single-channel memory controller that supports DDR2 memory in soldered down DRAM configurations only. The memory controller supports data rates of 800 MT/s. There is no support for ECC in the memory controller. 6.1.1 DRAM Frequencies and Data Rates The memory controller supports the clock frequencies and data rates for DRAM listed in Table 67. Table 67. 6.
Memory Controller 6.4.1 Powerdown Modes The memory controller employs aggressive use of memory power management features. When a rank is not being accessed, the CKE for that rank is deasserted, bringing the devices into a Power Down state. The memory controller supports Fast Power Down for DDR2 DRAMs. 6.4.2 Self Refresh Mode Self Refresh can be used to retain data in the DRAM devices, even if the remainder of the system is powered down.
Memory Controller 6.6 Supported DRAM Configurations The memory controller supports a single, 32-bit channel and up to eight soldered down DDR2 DRAM devices. The memory controller does not support SODIMM or any type of DIMMs. Table 68 shows the different supported memory configurationsIntel® Atom™ Processor E6x5C Series-based – Platform Design Guide. Table 68.
Memory Controller 6.7 Supported DRAM Devices Table 69.
Memory Controller 6.9 Address Mapping and Decoding For any rank, the address range it implements is mapped into the physical address regions of the devices on that rank. This is addressable by bank (B), row (R), and column (C) addresses. Once a rank is selected as described above, the range that it is implementing is mapped into the device’s physical address as described in Table 71. Table 71.
Memory Controller Table 71.
Graphics, Video, and Display 7.0 Graphics, Video, and Display 7.1 Chapter Contents This chapter contains the following information: • Overview • 3D Core Key Features • Video Encode Overview • Video Decode Overview • Display Overview • Register Description 7.2 Overview The Intel® Atom™ Processor E6xx Series contains an integrated graphics engine, video decode and encode capabilities, and a display controller that can support one LVDS display and one SDVO display (see Figure 5). Figure 5.
Graphics, Video, and Display — 3D peak performance — Fill rate: two pixels per clock — Vertex rate: One triangle 15 clocks (transform only) — Vertex/Triangle ratio average = 1 vtx/tri, peak 0.5 vtx/tri • Texture maximum size = 2048 x 2048 • Programmable 4x multi-sampling anti-aliasing (MSAA) — Rotated grid — ISP performance related to AA mode, TSP performance unaffected by AA mode • Optimized memory efficiency using multi-level cache architecture 7.2.
Graphics, Video, and Display 7.2.3 Vertex Processing Modern graphics processors perform two main procedures to generate 3D graphics. First, vertex geometry information is transformed and lit to create a 2D representation in the screen space. Those transformed and lit vertices are then processed to create display lists in memory. The pixel processor then rasterizes these display lists on a regional basis to create the final image.
Graphics, Video, and Display calculate specular lighting than diffuse lighting, it adds significant detail to the surface of some objects. • Emissive lighting is light that is emitted by an object, such as a light bulb. 7.2.4 Pixel Processing After vertices are transformed and lit by the vertex processing pipeline, the pixel processor takes the vertex information and generates the final rasterized pixels to be displayed.
Graphics, Video, and Display four 8-bit values. When considered as four 8-bit values, the integer unit effectively acts like a four-way SIMD ALU, performing four operations per clock. It is expected that in legacy applications pixel processing will be done on 8-bit integers, roughly quadrupling the pixel throughput compared to processing on float formats. 7.2.
Graphics, Video, and Display 7.3.1.2 Encode Codec Support The Intel® Atom™ Processor E6xx Series supports the following profiles and levels as shown in Table 72. Table 72. 7.3.1.3 Encode Profiles and Levels of Support Standard Profile Maximum Bit Rate (bps) Typical Picture and Frame Rate H.264 BP 128K QCIF @15 fps H.264 BP 192K QCIF @30 fps H.264 BP 384K CIF @15 fps or QVGA @ 20 fps H.264 BP 2M CIF @ 30 fps or QVGA @ 30 fps H.
Graphics, Video, and Display 7.4 Video Decode The video decode accelerator improves video performance/power by providing hardware-based acceleration at the macroblock level (variable length decode stage entry point). The Intel® Atom™ Processor E6xx Series supports full hardware acceleration of the following video decode standards. Table 73. Hardware Accelerated Video Decoding Support Codec Profile Level H.264 Baseline profile L3 H.264 Main profile L4.1 (1080p @ 30 fps) H.264 High profile L4.
Graphics, Video, and Display 7.4.1.1 Motion Compensation The entropy encoder or host can write a series of commands to define the type of motion predication used. The motion predicated data is then combined with residual data, and the resulting reconstructed data is passed to the de-blocker. The Motion Compensation module is made-up of four sub-modules: • The Module Control Unit module controls the overall motion compensation operation.
Graphics, Video, and Display 7.4.1.4 Pixel Format The pixel format has the name 420PL12YUV8. This consists of a single plane of luma (Y) and a second plane consisting of interleaved Cr/Cb (V/U) components. For 420PL12YUV8, the number of chroma samples is a quarter of the quantity of luma samples—half as many vertically, half as many horizontally. See Table 74 and Table 75 for pixel formats. Table 74. Table 75.
Graphics, Video, and Display LVDS display devices (see Figure 6). Along the display pipe, the display data can be converted from one format to another, stretched or shrunk, and color corrected or gamma converted. Figure 6.
Graphics, Video, and Display • Supports NV12 data format • 3x3 Panel Fitter shared by two pipes • Support Constant Alpha mode on Display C/Video sprite plane • DPST 3.0 The display contains the following functions: • Display data fetching • Out of order display data handling • Display blending • Gamma correction • Panel fitter function 7.5.
Graphics, Video, and Display Note: The Intel® Atom™ Processor E6xx Series has limited support for a VGA Plane. The VGA plane is suitable for usages, such as BIOS boot screens, pre-OS splash screens, etc. Other usages of the VGA plane (like DOS-based games, for example) are not supported. 7.5.1.2 Display Pipes The display consists of two pipes: • Display Pipe A • Display Pipe B A pipe consists of a set of combined planes and a timing generator.
Graphics, Video, and Display Figure 7. Display Resolutions 7.5.2.1 LVDS Port A single LVDS channel only is supported. The single LVDS channel can support clock frequency ranges up to a maximum pixel clock rate up to 80 MHz. The graphics core is responsible to read the EDID ROM from the installed panel (if present) specifications through I2C* interface and the software driver uses it to program the pipe A timing registers.
Graphics, Video, and Display transmitter port at the dot clock frequency, which is determined by the panel timing requirements. The serialized output of LVDS is running at the serial clock of 7x dot clock frequency. The transmitter can operate in a variety of modes and supports several data formats. The serializer supports 6-bit or 8-bit color per lane (for 18-bit and 24-bit color respectively) and single-channel operating modes.
Graphics, Video, and Display A maximum pixel clock of 160 MHz is supported on the SDVO interface. 7.5.2.4 SDVO DVI/HDMI DVI (and HDMI), a 3.3-V interface standard supporting the TMDS protocol, is a prime candidate for SDVO. The Intel® Atom™ Processor E6xx Series provides an unscaled mode where the display data is centered within the attached display area. Monitor Hot Plug functionality is supported. 7.5.2.4.
Graphics, Video, and Display 7.7 Configuration Registers 7.7.1 D2:F0 PCI Configuration Registers Table 76. PCI Header for D2 Offset Register Description 00h GVD.ID D2: PCI Device and Vendor ID Register 04h GVD.PCICMDSTS PCI Command and Status Register 08h GVD.RIDCC Revision Identification and Class Codes 0Ch GVD.HDR Header Type 10h GVD.MMADR Memory Mapped Address Range. This is the base address for all memory mapped registers. 14h GVD.GFX_IOBAR I/O Base Address.
Graphics, Video, and Display Table 77. 00h: GVD.ID – D2: PCI Device and Vendor ID Register Size: 32 bit Default: 41088086h Access Bit Range Default PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access Acronym Power Well: Core Offset Start: 00h Offset End: 01h Register Address: 00h Description 31 :20 410h RO DIDH: Identifier assigned to the Device 2 Graphics PCI device. Bits[31:20] of this register are strapped at the processor top level.
Graphics, Video, and Display Table 78. 04h: GVD.PCICMDSTS – PCI Command and Status Register (Sheet 2 of 2) Size: 32 bit Default: 00100000h Access Bit Range Default 0 0b Table 79. PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access RW Acronym Power Well: Core Offset Start: 04h Offset End: Register Address: 01h Description IOSE: When set, accesses to this device’s I/O space is enabled. When 1, the GVD will check if scldown3_address[15:0] is in the VGA IO range.
Graphics, Video, and Display Table 81. 10h: GVD.MMADR – Memory Mapped Address Range Size: 32 bit Default: 00000000h Access Bit Range Default 31 :20 19 :1 000h PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access RW 0000h RO 0b RO 0 Table 82. Bit Range Default 2 :1 0 Register 04h Address: Description BA: Set by the OS, these bits correspond to address signals [31:20]. The GVD will compare the SCL address scldown3_address[31:20] with MMADR[31:20].
Graphics, Video, and Display Table 83. 18h: GVD.GMADR – Graphics Memory Address Range Size: 32 bit Default: 00000000h Access Bit Range Default PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access Acronym Power Well: Core Offset Start: 18h Offset End: Register Address: 06h Description 0h RW BA: Set by the OS, these bits correspond to address signals [31:28]. The GVD will compare the SCL address scldown3_address[31:29,28, or 27] with GMADR[31:29,28, or 27], respectively.
Graphics, Video, and Display Table 85. 2Ch: GVD.SSID – Subsystem Identifiers Size: 32 bit Default: 00000000h Access Bit Range Default 31 0 0h Table 86. PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access WOARnROAW Access Bit Range Default The value in this field is programmed by the system BIOS. According to the PCI spec, only the BIOS can write it, and only once after reset. After SUBSYSTEM_ID the first write, this register becomes read-only.
Graphics, Video, and Display Table 88. 50h: GVD.
Graphics, Video, and Display Table 89. 5Ch: GVD.BSM – Base of Stolen Memory Size: 32 bit Default: 00000000h Access Bit Range Default 31 :20 19 :0 PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access 000h RW 00000h RO Table 90. Access Bit Range Default 15 :0 0000h BSM: This register contains bits 31 to 20 of the base address of stolen DRAM memory.
Graphics, Video, and Display Table 91. 90h: GVD.MSI_CAPID – Message Signaled Interrupts Capability ID and Control Register (Sheet 2 of 2) Size: 32 bit Default: 00000005h Access Bit Range Default PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access Acronym Power Well: Core Offset Start: 90h Offset End: Register Address: 24h Description 22 :20 000b RW MULTIPLE_MES MME: This field is RW for software compatibility, but only a single SAGE_ENABLE message is ever generated.
Graphics, Video, and Display Table 94. B0h: GVD.VCID – Vendor Capability ID Size: 32 bit Default: 01070009h Access Bit Range Default 31 :24 01h PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Power Well: Core Offset Start: B0h Offset End: Register Address: 2Ch Access Acronym Description RO VERSION VS: Identifies this as the first revision of the CAPID register definition. LENGTH LEN: This field has the value 07h to indicate the structure length (8 bytes).
Graphics, Video, and Display Table 97. D0h: GVD.PMCAP – Power Management Capabilities Size: 32 bit Default: 0022B001h Access Bit Range Default 31 :27 26 25 PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access Acronym Power Well: Core Offset Start: D0h Offset End: Register Address: 34h Description 00h RO 0b RO PME_SUPPORT PMES The graphics controller does not generate PME#. D2_SUPPORT D2S: The D2 power management state is not supported.
Graphics, Video, and Display Table 99. E0h: GVD.SWSMISCI – Software SMI or SCI (Sheet 2 of 2) Size: 32 bit Default: 00000000h Access Bit Range Default 0 0b Table 100. PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Access RW Bit Range Default 15 :8 7 :0 00h 00h 00h 00h Table 101. Description MCE: If MCS=1, setting this bit causes an SCI. If MCS=0, setting this bit SMI_OR_SCI_E causes an SMI. A 1 to 0, 0 to 0 or 1 to 1 transition of this bit does not VENT trigger any events.
Graphics, Video, and Display Table 101. F4h: GVD.LBB – Legacy Backlight Brightness (Sheet 2 of 2) Size: 32 bit Default: 00000000h Access PCI Configuration B:D:F 0:2:0 Message Bus Port: 06h Bit Range Default Access Acronym Power Well: Core Offset Start: F4h Offset End: Register Address: 39h Description 23 :16 00h RW SCRATCH_2 Software scratch byte 2.
Graphics, Video, and Display Table 103.
Graphics, Video, and Display Table 105. Offset 04h: CMD – PCI Command (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 00 0 B:D:F 0:3:0 Access Acronym RW IOSE I/O Space Enable: When set, accesses to this device’s I/O space is enabled. Offset 06h: STS - PCI Status Table 106.
Graphics, Video, and Display Table 108. Offset 09h: CC - Class Codes (Sheet 2 of 2) Size: 24 bit Default: 00000000h Access PCI Configuration Bit Range Default B:D:F 0:3:0 Acronym Description Sub-Class Code: When GC.VD is cleared, this value is 00h. When GC.VD is set, this value is 80h. 00h/80 h RO SCC 07 : 00 00h RO PI Programming Interface: Indicates a display controller. 7.7.2.6 Offset 0Eh: HDR - Header Type Table 109.
Graphics, Video, and Display 7.7.2.8 Offset 14h: IOBAR - I/O Base Address This register provides the base offset of 8 bytes of I/O registers within this device. Access to I/O space is allowed in the D0 state when CMD.IOSE is set. Access is disallowed in states D1-D3 or if CMD.IOSE is cleared. Access to this space is independent of VGA functionality. Table 111.
Graphics, Video, and Display 7.7.2.12 Offset 58h: SSRW - Software Scratch Read Write Table 114. Offset 58h: SSRW - Software Scratch Read Write Size: 32 bit Default: 00000000h Access PCI Configuration Bit Range Default 31 : 00 00h Power Well: Core Offset Start: 58h Offset End: 5Bh B:D:F 0:3:0 Access Acronym RO S Description Scratch: Scratchpad bits. 7.7.2.13 Offset 60h: HSRW - Hardware Scratch Read Write Table 115.
Graphics, Video, and Display Table 117. Offset 92h: MC - Message Control (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 00 0 Access RW Power Well: Core Offset Start: 92h Offset End: 93h B:D:F 0:3:0 Acronym Description MSIE MSI Enable: If set, MSI is enabled and traditional interrupts are not used to generate interrupts. CMD.BME must be set for an MSI to be generated.
Graphics, Video, and Display Table 120. Offset C4h: FD - Functional Disable (Sheet 2 of 2) Size: 32 bit Default: 00000000h Access PCI Configuration Bit Range Default 00 0h Power Well: Core Offset Start: C4h Offset End: C7h B:D:F 0:3:0 Access Acronym RW D Description Disable: When set, the function is disabled (configuration space is disabled). 7.7.2.19 Offset E0h: SWSCISMI - Software SCI/SMI Table 121.
Graphics, Video, and Display Table 123. Offset F0h: GCR - Graphics Clock Ratio (Sheet 2 of 2) Size: 16 bit Default: 0006h Access PCI Configuration Bit Range Default Access 03 : 02 01 RW 01 : 00 10 RW Power Well: Core Offset Start: F0h Offset End: F1h B:D:F 0:3:0 Acronym Description graphics 2x Clock to Graphics Clock Ratio: This field should be set by software to correspond with the gfx2xclkp (graphics 2x clock) to gfxclkp (graphics clock) ratio.
PCI Express* 8.0 PCI Express* 8.1 Functional Description There are four PCI Express* root ports available in the Intel® Atom™ Processor E6xx Series. They reside in device 23, 24, 25, and 26, and all take function 0. Port 0 is device 23, Port 1 is device 24, Port 2 is device 25 and Port 3 is device 26. 8.1.1 Interrupt Generation The processor generates interrupts on behalf of hot plug and power management events, when enabled. These interrupts can either be pin-based or can be MSIs.
PCI Express* If RCTL.PIE is set, an interrupt is generated. If RCTL.PIE is not set, an SCI/SMI_B may be set. If RSTS.PS is set, and RCTL.PIE is later written from a ‘0’ to a ‘1,’ an interrupt is generated. 8.1.2.4 SMI/SCI Generation To support power management on non PCI Express* aware operating systems, power management events can be routed to generate SCI, by setting MPC.PMCE. In addition, RTSTS.PS and PMCES.PME must be set and root port must be in D3hot power state (by setting PMCS.
PCI Express* Table 126.
PCI Express* Table 128. Offset 02h: DID — Device Identification Size: 16 bit Default: Access PCI Configuration Bit Range Default 15 : 00 Access RO Power Well: Core B:D:F 0:23-26:0 Acronym DID(UB) Description Device Identification Number: Identifier assigned to the device (virtual PCI-to-PCI bridge) PCIe* Device 23 = 8184h PCIe* Device 24 = 8185h PCIe* Device 25 = 8180h PCIe* Device 26 = 8181h 8.2.1.3 CMD — PCI Command Table 129.
PCI Express* Table 130. Offset 06h: PSTS — Primary Status Size: 16 bit Default: 0010h Access PCI Configuration Bit Range Default 15 0b 14 B:D:F 0:23-26:0 Access Acronym RO RSVD Power Well: Core Offset Start: 6h Offset End: 7h Description Reserved Signaled System Error: This bit is set when this device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is ‘1.
PCI Express* 8.2.1.7 CLS — Cache Line Size Table 133. Offset 0Ch: CLS — Cache Line Size Size: 8 bit Default: 00h Access PCI Configuration Bit Range Default 07 : 00 00h 8.2.1.8 B:D:F 0:23-26:0 Power Well: Core Offset Start: Ch Offset End: Ch Access Acronym Description RW CLS Cache Line Size: Implemented by PCI Express* devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express* device functionality.
PCI Express* Table 136. Offset 19h: SCBN — Secondary Bus Number Size: 8 bit Default: 00h Access PCI Configuration Bit Range Default 07 : 00 00h 8.2.1.11 Power Well: Core Offset Start: 19h Offset End: 19h B:D:F 0:23-26:0 Access Acronym RW SCBN Description Secondary Bus Number: This field is programmed by configuration software with the bus number assigned to the PCI Express* device.
PCI Express* 8.2.1.13 IOLIMIT — I/O Limit Address This register controls the CPU to PCI Express* I/O access routing based on the following formula: IO_BASE =< address =< IO_LIMIT. Only the upper four bits are programmable. For the purpose of address decode, address bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4 kB aligned address block. Table 139.
PCI Express* Table 140. Offset 1Eh: SSTS — Secondary Status (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 07 : 00 000000 00b 8.2.1.15 Power Well: Core Offset Start: 1Eh Offset End: 1Fh B:D:F 0:23-26:0 Access Acronym RO RSVD Description Reserved MB — Memory Base Address Accesses that are within the ranges specified in this register and the ML register will be sent to the attached device if the Memory Space Enable bit of PCICMD is set.
PCI Express* Table 143. Offset 24h: PMB — Prefetchable Memory Base Address Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default B:D:F 0:23-26:0 Offset Start: 24h Offset End: 25h Access Acronym Description Prefetchable Memory Base Address: This corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express*. 15 : 04 000h RW PMB 03 : 00 0h RW RSVD 8.2.1.
PCI Express* Table 146. Offset 3Ch: ILINE — Interrupt Line Size: 8 bit Default: 00h Access PCI Configuration Bit Range Default 07 : 00 00h 8.2.1.21 B:D:F 0:23-26:0 Power Well: Core Offset Start: 3Ch Offset End: 3Ch Access Acronym Description RW ILINE Interrupt Line: This software written value indicates to which interrupt line (vector) the interrupt is connected. No hardware action is taken on this register. IPIN — Interrupt Pin This register specifies which interrupt pin this device uses.
PCI Express* Table 148. Offset 3Eh: BCTRL — Bridge Control (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 05 04 03 0b 0b Offset Start: 3Eh Offset End: 3Fh B:D:F 0:23-26:0 Access Acronym RO MAM Master Abort Mode: Reserved per PCI Express* spec. V16 VGA 16-Bit Decode: When set, this indicates that the I/O aliases of the VGA range (see BCTRL.VE definition below) are not enabled and only the base I/O ranges can be decoded.
PCI Express* 8.2.2.1 CLIST — Capabilities List Table 150. Offset 40h: CLIST — Capabilities List Size: 16 bit Default: 9010h Access PCI Configuration Bit Range Default Power Well: Core Offset Start: 40h Offset End: 41h B:D:F 0:23-26:0 Access Acronym 15 : 08 90h RO NEXT 07 : 00 10h RO CID Description Next Capability: Value of 90h indicates the location of the next pointer. Capability ID: This indicates this is a PCI Express* capability. 8.2.2.
PCI Express* Table 152. Offset 44h: DCAP — Device Capabilities (Sheet 2 of 2) Size: 32 bit Default: 00008FC0h Access PCI Configuration Bit Range Default B:D:F 0:23-26:0 Access Acronym Power Well: Core Offset Start: 44h Offset End: 47h Description 11 : 09 111b RO E1AL Endpoint L1 Acceptable Latency: This indicates more than 4 µs. This field essentially has no meaning for root ports since root ports are not endpoints.
PCI Express* 8.2.2.5 DSTS — Device Status Table 154. Offset 4Ah: DSTS — Device Status Size: 16 bit Default: 0010h Access PCI Configuration Bit Range Default 15 : 06 0 B:D:F 0:23-26:0 Access Acronym RO RSVD Power Well: Core Offset Start: 4Ah Offset End: 4Bh Description Reserved 05 0 RO TDP Transactions Pending: This bit has no meaning for the root port since only one transaction may be pending to the processor. A read of this cannot occur until it has already returned to ‘0.
PCI Express* 8.2.2.7 LCTL — Link Control Table 156. Offset 50h: LCTL — Link Control Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 15 : 0 B:D:F 0:23-26:0 Access Acronym RO RSVD Power Well: Core Offset Start: 50h Offset End: 51h Description Reserved Extended Synch: When set, this forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0.
PCI Express* 8.2.2.9 SLCAP — Slot Capabilities Table 158. Offset 54h: SLCAP — Slot Capabilities Size: 32 bit Default: 00000060h Access PCI Configuration Bit Range Default Access Acronym Description Physical Slot Number: This is a value that is unique to the slot number. The BIOS sets this field and it remains set until a platform reset.
PCI Express* Table 159. Offset 58h: SLCTL — Slot Control (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default B:D:F 0:23-26:0 Access Acronym Power Well: Core Offset Start: 58h Offset End: 59h Description 03 0b RW PDE Presence Detect Changed Enable: When set, enables the generation of a hot plug interrupt or wake message when the presence detect logic changes state.
PCI Express* 8.2.2.12 RCTL — Root Control Table 161. Offset 5Ch: RCTL — Root Control Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 15 : 04 0 B:D:F 0:23-26:0 Access Acronym RO RSVD Power Well: Core Offset Start: 5Ch Offset End: 5Bh Description Reserved 03 0 RW PIE PME Interrupt Enable: When set, this enables interrupt generation when RSTS.PS is in a set state (either due to a ‘0’ to ‘1’ transition, or due to this bit being set with RSTS.PS already set).
PCI Express* 8.2.3 PCI Bridge Vendor Capability Table 164. PCI Bridge Vendor Capability Start End Symbol 90 91 SVCAP 94 97 SVID Register Name Subsystem Vendor Capability ID Subsystem Vendor IDs 8.2.3.1 SVCAP — Subsystem Vendor Capability Table 165.
PCI Express* 8.2.4.1 PMCAP — Power Management Capability ID Table 168. Offset A0h: PMCAP — Power Management Capability ID Size: 16 bit Default: 0001h Access PCI Configuration Bit Range Default 15 : 08 00h 07 : 00 01h Offset Start: A0h Offset End: A1h B:D:F 0:23-26:0 Access Acronym RO NEXT RO Power Well: Core Description Next Capability: Last item in the list Capability Identifier: The value of 01h indicates that this is a PCI power management capability. CID 8.2.4.
PCI Express* Table 170. Offset A4h: PMCS — PCI Power Management Control And Status (Sheet 2 of 2) Size: 32 bit Default: 00000000h Access PCI Configuration Bit Range Default 08 07 : 02 01 : 00 B:D:F 0:23-26:0 Power Well: Core Offset Start: A4h Offset End: A7h Access Acronym Description 0 RW PMEE PME Enable: The root port takes no action on this bit, but it must be RW for legacy Microsoft* operating systems to enable PME on devices connected to this root port. 0 RO RSVD 00 RW PS 8.2.
PCI Express* 8.2.5.1 MPC — Miscellaneous Port Configuration Table 172. Offset D8h: MPC — Miscellaneous Port Configuration Size: 32 bit Default: 00110000h Access PCI Configuration Bit Range Default B:D:F 0:23-26:0 Access Acronym Power Well: Core Offset Start: D8h Offset End: DBh Description 31 0 RW PMCE Power Management SCI Enable: This enables SCI for power management events. 30 0 RW HPCE Hot Plug SCI Enable: This enables SCI for hot plug events.
PCI Express* 8.2.5.2 SMSCS — SMI / SCI Status Table 173. Offset DCh: SMSCS — SMI / SCI Status Size: 32 bit Default: 00000000h Access PCI Configuration Bit Range Default B:D:F 0:23-26:0 Power Well: Core Offset Start: DCh Offset End: DFh Access Acronym Description 31 0 RWC PMCS Power Management SCI Status: This is set if the root port PME control logic needs to generate an interrupt and this interrupt has been routed to generate an SCI.
PCI Express* 8.2.6 Miscellaneous Configuration Table 174. Miscellaneous Configuration Start FC End FF Symbol FD Register Name Functional Disable 8.2.6.1 FD — Functional Disable Table 175.
PCI Express* Intel® Atom™ Processor E6xx Series Datasheet 136
Intel® High Definition Audioβ D27:F0 9.0 Intel® High Definition Audioβ D27:F0 9.1 Overview The Intel® High Definition Audioβ controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external codec(s). The controller communicates with the external codec(s) over the Intel® HD Audioβ serial link. The Intel® Atom™ Processor E6xx Series implements two output DMA engines and two input DMA engines.
Intel® High Definition Audioβ D27:F0 Prior to the physical undocking process the user normally requests undocking. Software then gracefully halts the streams to the codecs in the docking station and then initiates the undocking sequence in the Intel® HD Audioβ controller. Intel® HD Audioβ controller asserts dock reset and then manages the external switch to electrically isolate the dock codec from the processor’s Intel® HD Audioβ interface prior to physical undocking.
Intel® High Definition Audioβ D27:F0 9.2.2 Undock Sequence There are two possible undocking scenarios. The first is the one that is initiated by the user that invokes software and gracefully shuts down the dock codecs before they are undocked. The second is referred to as the “surprise undock” where the user undocks while the dock codec is running. Both of these situations appear the same to the controller as it is not cognizant of the “surprise removal”. 1.
Intel® High Definition Audioβ D27:F0 9.2.4 External Pull-Ups/Pull-Downs The following table shows the resistors that should be mounted on the dock side of the isolation switch. The resistors are used to discharge the signals to reduce the chance of getting charge-sharing induced glitches when the switch is turned on via HDA_DOCK_EN_B assertion. Pull-downs have been specified to match the level of the signals when HDA_DOCK_EN_B is asserted as well as to not conflict with the internal resistors. Table 176.
Intel® High Definition Audioβ D27:F0 Intel® High Definition Audioβ PCI Configuration Registers (Sheet 2 of 3) Table 177.
Intel® High Definition Audioβ D27:F0 Intel® High Definition Audioβ PCI Configuration Registers (Sheet 3 of 3) Table 177. Start End Symbol Register Name Reset Value Access 134 137 ESD Element Self Description 0F00_0100h RO 140 143 L1DESC Link 1 Description 0000_0001 RO 148 14B L1ADD Link 1 Address Register Variable RW, RO 9.3.1.1 Offset 00h: VID – Vendor Identification Table 178.
Intel® High Definition Audioβ D27:F0 Table 180. 04h: PCICMD – PCI Command Register (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 00 0 Power Well: Core Offset Start: 04h Offset End: 05h B:D:F 0:27:0 Access Acronym RO RSVD Description Reserved 9.3.1.4 Offset 06h: PCISTS – PCI Status Register Table 181.
Intel® High Definition Audioβ D27:F0 Table 183. 09h: CC – Class Codes Register (Sheet 2 of 2) Size: 24 bit Access Power Well: Core B:D:F 0:27:0 Offset Start: 09h Offset End: 0Bh PCI Configuration Bit Range Default 07 :00 Default: 040300h 00h Access Acronym RO PI Description Programming Interface: Indicates Intel® HD Audioβ programming interface. 9.3.1.7 Offset 0Ch: CLS - Cache Line Size Register Table 184.
Intel® High Definition Audioβ D27:F0 Table 187. 10h: LBAR – Lower Base Address Register Size: 32 bit Default: 00000004h Access PCI Configuration Bit Range Default 31 :14 0 13 :04 Acronym RW LBA Lower Base Address: Base address for the Intel® HD Audioβ controller’s memory mapped configuration registers. 16 Kbytes are requested by hardwiring bits 13:4 to 0’s. Prefetchable: Indicates that this BAR is NOT pre-fetchable.
Intel® High Definition Audioβ D27:F0 9.3.1.13 Offset 2Eh: SID—Subsystem Identifier This register should be implemented for any function that could be instantiated more than once in a given system, for example, a system with 2 audio subsystems, one down on the motherboard and the other plugged into a PCI expansion slot. The SID register, in combination with the Subsystem Vendor ID register make it possible for the operating environment to distinguish one audio subsystem from the other.
Intel® High Definition Audioβ D27:F0 9.3.1.16 Offset 3Dh – INTPN—Interrupt Pin Register Table 193. 3Dh – INTPN — Interrupt Pin Register Size: 8 bit Default: Variable Access PCI Configuration Bit Range Default B:D:F 0:27:0 Access Acronym RSVD 07 :04 0 RO 03 :00 0 RO Power Well: Core Offset Start: 3Dh Offset End: 3Dh Description Reserved Interrupt Pin: This reflects the value of D27IP.ZIP (Chipset Config Registers: Offset 3110h:bits 3:0). 9.3.1.
Intel® High Definition Audioβ D27:F0 9.3.1.19 Offset 4Dh – DCKSTS—Docking Status Register Table 196. 4Dh: DCKSTS – Docking Status Register Size: 8 bit Default: 80h Access PCI Configuration Bit Range Default 07 06 :01 00 Access B:D:F 0:27:0 Description Docking Supported: A 1 indicates that the processor supports Intel® HD Audioβ Docking. The DCKCTL.DA bit is only writable when this DS bit is 1. Intel® HD Audioβ driver software should only branch to its docking routine when this DS bit is 1.
Intel® High Definition Audioβ D27:F0 Table 198. 52h: PM_CAP – Power Management Capabilities Register (Sheet 2 of 2) Size: 16 bit Default: 4802h Access PCI Configuration Bit Range Default 10 :03 02 :00 0 010 B:D:F 0:27:0 Access Acronym RO RSVD RO Power Well: Core Offset Start: 52h Offset End: 53h Description Reserved Version: Indicates support for Revision 1.1 of the PCI Power Management Specification. VS 9.3.1.
Intel® High Definition Audioβ D27:F0 9.3.1.23 Offset 60h: MSI_CAPID - MSI Capability ID Register Table 200. 60h: MSI_CAPID - MSI Capability ID Register Size: 16 bit Default: 0005h Access PCI Configuration Bit Range Default B:D:F 0:27:0 Access Acronym 15 :08 00h RO NEXT 07 :00 05h RO CAP Power Well: Core Offset Start: 60h Offset End: 61h Description Next Capability: Points to the next item in the capability list. Wired to 00h to indicate this is the last capability in the list.
Intel® High Definition Audioβ D27:F0 9.3.1.27 Offset 70h: PCIE_CAPID – PCI Express* Capability Identifiers Register Table 204. 70h: PCIE_CAPID – PCI Express* Capability Identifiers Register Size: 16 bit Default: 10h Access PCI Configuration Bit Range Default Access B:D:F 0:27:0 Power Well: Core Offset Start: 70h Offset End: 71h Acronym Description 15 :08 60h/00 h RO NEXT Next Capability: Defaults to 60h, the address of the next capability structure in the list. However, if the FD.
Intel® High Definition Audioβ D27:F0 Table 207. 78h: DEVC – Device Control (Sheet 2 of 2) Size: 16 bit Default: 0800h Access PCI Configuration Bit Range Default 14 :12 000 11 B:D:F 0:27:0 Access Acronym RO MRRS Power Well: Core Offset Start: 78h Offset End: 79h Description Max Read Request Size: Hardwired to 000 enabling 128 B maximum read request size. Enable No Snoop: 0 = The Intel® HD Audioβ controller will not set the No Snoop bit.
Intel® High Definition Audioβ D27:F0 Table 209. FCh – FD: Function Disable Register (Sheet 2 of 2) Size: 32 bit Default: 0000_0000h Access PCI Configuration Bit Range Default Power Well: Core Offset Start: FCh Offset End: FFh B:D:F 0:27:0 Access Acronym 02 0 RW GCD 01 0 RW MD 00 0 RW D Description Clock Gating Disable: 0 = Clock gating within the device is enabled (Default) 1 = Clock gating within the device is disabled. MSI Disable: 0 = The MSI capability is visible.
Intel® High Definition Audioβ D27:F0 9.3.1.35 Offset 108h: PVCCAP2 – Port VC Capability Register 2 Table 212. 108h: PVCCAP2 – Port VC Capability Register 2 Size: 32 bit Default: 0000 0000h Access PCI Configuration Bit Range Default 31 :00 0 B:D:F 0:27:0 Access Acronym RO RSVD Power Well: Core Offset Start: 108h Offset End: 10Bh Description Reserved 9.3.1.36 Offset 10Ch: PVCCTL – Port VC Control Register Table 213.
Intel® High Definition Audioβ D27:F0 9.3.1.39 Offset 114h: VC0CTL – VC0 Resource Control Register Table 216. 114h: VC0CTL – VC0 Resource Control Register Size: 32 bit Default: 8000 00FFh Access PCI Configuration Bit Range Default 31 30 :08 07 :00 Acronym 1 RO VC0EN 0 RO RSVD RW/RO Offset Start: 114h Offset End: 117h B:D:F 0:27:0 Access FFh Power Well: Core VC0MAP Description VC0 Enable: Hardwired to 1 for VC0.
Intel® High Definition Audioβ D27:F0 Table 219. 120h: VC1CTL – VC1 Resource Control Register (Sheet 2 of 2) Size: 32 bit Default: 0000_0000h Access PCI Configuration Bit Range Default 23 :08 0 07 :00 00h Power Well: Core Offset Start: 120h Offset End: 123h B:D:F 0:27:0 Access Acronym RO RSVD Description Reserved TC/VC Map: This field indicates the TCs that are mapped to the VC1 resource. Bit 0 is hardwired to 0 indicating it can not be mapped to VC1. Bits [7:1] are implemented as RW bits.
Intel® High Definition Audioβ D27:F0 Table 222. 134h: ESD – Element Self Description Register (Sheet 2 of 2) Size: 32 bit Default: 0F00_0100h Access PCI Configuration Bit Range Default Power Well: Core Offset Start: 134h Offset End: 137h B:D:F 0:27:0 Access Acronym Description Number of Link Entries: The Intel® HD Audioβ controller only connects to one device, the processor egress port. Therefore this field reports a value of 1h.
Intel® High Definition Audioβ D27:F0 These memory mapped registers must be accessed a byte, word, or Dword quantities. Addresses not shown must be treated as reserved. Table 225.
Intel® High Definition Audioβ D27:F0 Table 225.
Intel® High Definition Audioβ D27:F0 Intel® HD Audioβ Register Summary (Sheet 3 of 3) Table 225. Offset Start Offset End Symbol Full Name 20A4 20A7 ISD1LPIBA ISD1 Link Position in Buffer Alias 0000_0000h RO 2104 2107 OSD0LPIBA OSD0 Link Position in Buffer Alias 0000_0000h RO 2124 2127 OSD1LPIBA OSD1 Link Position in Buffer Alias 0000_0000h RO 9.3.2.1.1 Offset 00h: GCAP – Global Capabilities Register Table 226.
Intel® High Definition Audioβ D27:F0 9.3.2.1.3 Offset 03h: VMAJ – Major Version Table 228. 03h: VMAJ – Major Version Size: 8 bit Default: 01h Access PCI Configuration Memory Mapped IO Bit Range Default 07 :00 01h B:D:F 0:27:0 Power Well: Core Offset Start: 03h Offset End: 03h BAR: LBAR Access Acronym RO VMAJ Offset: Description Major Version: Indicates that the processor supports major revision number 1 of the Intel® HD Audioβ specification. 9.3.2.1.
Intel® High Definition Audioβ D27:F0 Table 230. 06h: INPAY – Input Payload Capability Register (Sheet 2 of 2) Size: 16 bit Default: 001Dh Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default 06 :00 1Dh Access RO BAR: LBAR INPAY Input Payload Capability: Indicates the total input payload available on the link. This does not include bandwidth used for response. This measurement is in 16-bit word quantities per 48 kHz frame. The default link clock speed of 24.
Intel® High Definition Audioβ D27:F0 Table 231. 08h: GCTL – Global Control (Sheet 2 of 2) Size: 32 bit Default: 0000_0000h Access PCI Configuration Memory Mapped IO Bit Range Default 00 0 Access RW B:D:F 0:27:0 BAR: LBAR CRST_B Controller Reset #: 0 = Writing a 0 to this bit causes the Intel® HD Audioβ controller to be reset. All state machines, FIFO’s and non-resume well memory mapped configuration registers (not PCI Configuration Registers) in the controller will be reset.
Intel® High Definition Audioβ D27:F0 9.3.2.1.8 Offset 0Eh: STATESTS – State Change Status Table 233. 0Eh: STATESTS – State Change Status Size: 16 bit Default: 0000h Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default 15 :02 01 :00 0 0 BAR: LBAR Access Acronym RO RSVD RWC SDIWAKE SDIN State Change Status Flags: Flag bits that indicate which SDI signal(s) received a “State Change” event. The bits are cleared by writing a 1 to them.
Intel® High Definition Audioβ D27:F0 9.3.2.1.10 Offset 14h: ECAP - Extended Capabilities Table 235. 14h: ECAP - Extended Capabilities Size: 32 bit Default: 0000_0000h Access PCI Configuration 31 :1 0 0 0h BAR: LBAR Access Acronym RO RSVD R/WO Offset Start: 14h Offset End: 17h B:D:F 0:27:0 Memory Mapped IO Bit Range Default Power Well: Core Offset: Description Reserved Docking Supported: A 1 indicates that processor supports Intel® HD Audioβ Docking. The GCTL.
Intel® High Definition Audioβ D27:F0 Table 237. 20h: INTCTL - Interrupt Control Register (Sheet 2 of 2) Size: 32 bit Default: 0000_0000h Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default 29 :04 03 :00 0 0h Acronym RO RSVD Reserved Stream Interrupt Enable: When set to 1 the individual Streams are enabled to generate an interrupt when the corresponding stream status (INTSTS) bits get set.
Intel® High Definition Audioβ D27:F0 Table 239. 30h: WALCLK – Wall Clock Counter Register Size: 32 bit Default: 0000_0000h Access PCI Configuration Memory Mapped IO Bit Range Default 31 :00 0000_ 0000h Access RO Power Well: Core Offset Start: 30h Offset End: 33h B:D:F 0:27:0 BAR: LBAR Offset: Acronym Description Counter Wall Clock Counter: 32 bit counter that is incremented on each link Bit Clock period and rolls over from FFFF_FFFFh to 0000_0000h.
Intel® High Definition Audioβ D27:F0 9.3.2.1.16 Offset 40h: CORBBASE - CORB Base Address Register Table 241.
Intel® High Definition Audioβ D27:F0 Table 243. 4Ah: CORBRP - CORB Read Pointer Register (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Memory Mapped IO Bit Range Default 07 :00 0 Access Power Well: Core Offset Start: 4Ah Offset End: 4Bh B:D:F 0:27:0 BAR: LBAR Offset: Acronym Description CORB Read Pointer: Software reads this field to determine how many commands it can write to the CORB without over-running.
Intel® High Definition Audioβ D27:F0 9.3.2.1.21 Offset 4Eh: CORBSIZE - CORB Size Register Table 246. 4Eh: CORBSIZE - CORB Size Register Size: 8 bit Default: 42h Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default Offset: Access Acronym Description CORB Size Capability: 0100b indicates that the processor only supports a CORB size of 256 CORB entries (1024B).
Intel® High Definition Audioβ D27:F0 9.3.2.1.24 Offset 5Ah: RINTCNT – Response Interrupt Count Register Table 249.
Intel® High Definition Audioβ D27:F0 9.3.2.1.26 Offset 5Dh: RIRBSTS - RIRB Status Register Table 251.
Intel® High Definition Audioβ D27:F0 9.3.2.1.28 Offset 60h: IC – Immediate Command Register Table 253. 60h: IC – Immediate Command Register Size: 32 bit Default: 0000_0000h Access PCI Configuration 31 :00 0 Offset Start: 60h Offset End: 63h B:D:F 0:27:0 Memory Mapped IO Bit Range Default Power Well: Core BAR: LBAR Offset: Access Acronym Description RW ICW Immediate Command Write: The command to be sent to the codec via the Immediate Command mechanism is written to this register.
Intel® High Definition Audioβ D27:F0 Table 255. 68h: ICS – Immediate Command Status (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default 00 0 Access RW Power Well: Core Offset Start: 68h Offset End: 69h BAR: LBAR Offset: Acronym Description ICB Immediate Command Busy: When this bit as read as a 0 it indicates that a new command may be issued using the Immediate Command mechanism.
Intel® High Definition Audioβ D27:F0 9.3.2.1.32 Offset 80h, A0h, C0h, E0h: ISD0CTL, ISD1CTL, OSD0CTL, OSD1CTL – Input/Output Stream Descriptor [0-1] Control Register Table 257.
Intel® High Definition Audioβ D27:F0 Table 257. 80h, A0h, C0h, E0h: ISD0CTL, ISD1CTL, OSD0CTL, OSD1CTL – Input/Output Stream Descriptor [0-1] Control Register (Sheet 2 of 2) Size: 24 bit Default: 04_0000h Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default 00 0 Access RW BAR: LBAR Power Well: Core Offset Start: 80h, A0h, C0h, E0h Offset End: 82h, A2h, C2h, E2h Offset: Acronym Description SRST Stream Reset: 0 = Writing a 0 causes the corresponding stream to exit reset.
Intel® High Definition Audioβ D27:F0 9.3.2.1.34 Offset 84h, A4h, C4h, E4h: ISD0LPIB, ISD1LPIB, OSD0LPIB, OSD1LPIB – Input/Output Stream Descriptor [0-1] Link Position in Buffer Register Table 259.
Intel® High Definition Audioβ D27:F0 Table 261.
Intel® High Definition Audioβ D27:F0 9.3.2.1.38 Offset 90h, B0h: ISD0FIFOS, ISD1FIFOS – Input Stream Descriptor [0-1] FIFO Size Register , Table 263.
Intel® High Definition Audioβ D27:F0 Table 264. D0h, F0h: OSD0FIFOS, OSD1FIFOS – Output Stream Descriptor [0-1] FIFO Size Register (Sheet 2 of 2) Size: 16 bit Default: 00BFh Access PCI Configuration Access Offset Start: D0h, F0h Offset End: D1h, F1h B:D:F 0:27:0 Memory Mapped IO Bit Range Default Power Well: Core BAR: LBAR Offset: Acronym Description FIFO Size: Indicates the maximum number of bytes that could be fetched by the controller at one time.
Intel® High Definition Audioβ D27:F0 Table 265. 92h, B2h, D2h, F2h: ISD0FMT, ISD1FMT, OSD0FMT, OSD1FMT – Input/Output Stream Descriptor [0-1] Format Register (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default 13 :11 10 :08 000b 03 :00 RW Offset Start: 92h, B2h, D2h, F2h Offset End: 93h, B3h, D3h, F3h BAR: LBAR Acronym MULT Offset: Description Sample Base Rate Multiple: 000=48 kHz/44.1 kHz or less 001=x2 (96 kHz, 88.
Intel® High Definition Audioβ D27:F0 Table 266.
Intel® High Definition Audioβ D27:F0 Table 267. 1000h: EM1 – Extended Mode 1 Register (Sheet 2 of 2) Size: 32 bit Default: 0000_0000h Access PCI Configuration B:D:F 0:27:0 Memory Mapped IO Bit Range Default Power Well: Core Offset Start: 1000h Offset End: 1003h BAR: Access Acronym Offset: Description 12 :11 0 RW RSVD Reserved 10 : 06 0 RO RSVD Reserved 05 :04 0 WO IRCR Input Repeat Count Resets: Software writes a 1 to clear the respective Repeat Count to 00h.
Intel® High Definition Audioβ D27:F0 9.3.2.1.45 Offset 100Ch: FIFOTRK – FIFO Tracking Register Table 270.
Intel® High Definition Audioβ D27:F0 9.3.2.1.47 Offset 1030h: EM2 – Extended Mode 2 Register Table 272.
Intel® High Definition Audioβ D27:F0 9.3.2.1.49 Offset 2084h, 20A4h, 2104h, 2124h: ISD0LPIBA, ISD1LPIBA, OSD0LPIBA, OSD1LPIBA – Input/Output Stream Descriptor [0-1] Link Position in Buffer Alias Register Table 274.
LPC Interface (D31:F0) 10.0 LPC Interface (D31:F0) 10.1 Functional Overview The LPC controller implements a low pin count interface that supports the LPC 1.1 specification: • LSMI_B can be connected to any of the SMI capable GPIO signals. • The EC’s PME_B should connect it to GPE_B. • The LPC controller’s SUS_STAT_B signal is connected directly to the LPCPD_B signal. The LPC controller does not implement DMA or bus mastering cycles. The LPC bridge function resides in PCI Device 31:Function 0.
LPC Interface (D31:F0) Note: By default, the LPC clocks are only active when LPC bus transfers occur. Because of this behavior, LPC clocks must be routed directly to the bus devices; they cannot go through a clock buffer or other circuit that could delay the signal going to the end device. 10.2 PCI Configuration Registers Note: Address locations that are not shown should be treated as Reserved. . Table 275.
LPC Interface (D31:F0) Table 276. Offset 00h: ID – Identifiers (Sheet 2 of 2) Size: 32 bit Default: 81868086h Access Bit Range PCI Configuration B:D:F X:31:0 Default Access Acronym 8086h RO VID 15 : 00 Vendor Identification: This is a 16-bit value assigned to Intel. CMD—Device Command Register Table 277.
LPC Interface (D31:F0) 10.2.5 CC—Class Code Register Table 280. Offset 09h: CC – Class Code Size: 24 bit Default: 060100h Access Bit Range PCI Configuration B:D:F X:31:0 Power Well: Offset Start: 09h Offset End: 0Bh Default Access Acronym Description 23 : 16 06h RO BCC Base Class Code: Indicates the device is a bridge device. 15 : 08 01h RO SCC Sub-Class Code: Indicates the device a PCI to ISA bridge.
LPC Interface (D31:F0) 10.3 ACPI Device Configuration 10.3.1 SMBA—SMBus Base Address Register Table 283. Offset 40h: SMBA – SMBus Base Address Size: 32 bit Default: 00000000h Access Bit Range PCI Configuration Access Acronym 0 RW EN 30 : 16 0h RO RSVD 15 : 06 0h RW BA 05 : 00 0h RO RSVD Description Enable: 1 = Decode of the I/O range pointed to by the SMBASE.BA field is enabled. Reserved. Base Address: This field provides the 64 bytes of I/O space for SMBus Reserved. 10.3.
LPC Interface (D31:F0) Table 285. Offset 48h: PM1BLK – PM1_BLK Base Address (Sheet 2 of 2) Size: 32 bit Default: 00000000h Access Bit Range PCI Configuration B:D:F X:31:0 Default Access Acronym 0h RO RSVD 03 : 00 Power Well: Offset Start: 48h Offset End: 4Bh Description Reserved. 10.3.4 GPE0BLK—GPE0_BLK Base Address Register Table 286.
LPC Interface (D31:F0) Table 287. Offset 54h: LPCS – LPC Clock Strength Control (Sheet 2 of 2) Size: 32 bit Default: Access Bit Range PCI Configuration Access Acronym Strap RW C04M Description Clock 0 4m Strength: Clock 0 4m Strength Control 10.3.6 ACTL—ACPI Control Register Table 288.
LPC Interface (D31:F0) Table 289. Offset 5Ch: MC – Miscellaneous Control (Sheet 2 of 3) Size: 32 bit Default: 00000000h Access Bit Range 23 : 21 PCI Configuration B:D:F X:31:0 Default Access Acronym 0h RO RSVD Reserved Power Well: Offset Start: 5Ch Offset End: 5Fh Description 0 RW BTC6 Block Timer Ticks in C6: When set, timer ticks will be blocked up to NTT while the processor is in the C6 state. If not set, timer ticks will not be blocked in the C6 state.
LPC Interface (D31:F0) Table 289. Offset 5Ch: MC – Miscellaneous Control (Sheet 3 of 3) Size: 32 bit Default: 00000000h Access Bit Range PCI Configuration Power Well: Offset Start: 5Ch Offset End: 5Fh B:D:F X:31:0 Default Access Acronym Description 02 0 RW D8259 Disable 8259: When set, decodes to the 8259 will be disabled, and the accesses instead will be sent to LPC. This allows testing to determine whether these functions are needed for XP and Vista.
LPC Interface (D31:F0) 10.4.2 SCNT—Serial IRQ Control Register Table 291. Offset 68h: SCNT – Serial IRQ Control Size: 8 bit Default: 80h Access Bit Range PCI Configuration Default 07 06 : 00 Access B:D:F X:31:0 Description Mode: This bit must be set to ensure that the first action of the processor is a start frame. 0 = Processor is in quiet mode 1 = Processor is in continuous mode RW MD 00h RO RSVD Reserved 10.4.3 WDTBA-WDT Base Address Table 292.
LPC Interface (D31:F0) Table 293. Offset D0h: FS – FWH ID Select (Sheet 2 of 2) Size: 32 bit Default: 00112233h Access Bit Range PCI Configuration B:D:F X:31:0 Power Well: Offset Start: D0h Offset End: D3h Default Access Acronym Description 27 : 24 0h RW IF0 F0-F7 IDSEL: IDSEL to use in FWH cycle for range enabled by BDE.EF0. The Address ranges are: FFF00000h – FFF7FFFFh, FFB00000h – FFB7FFFFh 23 : 20 1h RW IE8 E8-EF IDSEL: IDSEL to use in FWH cycle for range enabled by BDE.EE8.
LPC Interface (D31:F0) Table 294. Offset D4h: BDE – BIOS Decode Enable (Sheet 2 of 2) Size: 32 bit Default: FF000000h Access Bit Range PCI Configuration Power Well: Offset Start: D4h Offset End: D7h B:D:F X:31:0 Default Access Acronym 1b RW ED8 D8-DF Enable: Enables decoding of BIOS range FFD80000h – FFDFFFFFh and FF980000h – FF9FFFFFh. 0 = Disable, 1 = Enable 27 Description 26 1b RW ED0 D0-D7 Enable: Enables decoding of BIOS range FFD00000h – FFD7FFFFh and FF900000h – FF97FFFFh.
LPC Interface (D31:F0) Table 295. Offset D8h: BC – BIOS Control (Sheet 2 of 2) Size: 32 bit Default: 00000100h Access Bit Range PCI Configuration Power Well: Offset Start: D8h Offset End: DBh B:D:F X:31:0 Default Access Acronym Description 0b RW WP Write Protect: When set, access to BIOS is enabled for both read and write cycles. When cleared, only read cycles are permitted to BIOS. When written from a 0 to a 1 and LE is also set, an SMI_B is generated.
LPC Interface (D31:F0) Intel® Atom™ Processor E6xx Series Datasheet 200
ACPI Devices 11.0 ACPI Devices 11.1 8254 Timer The 8254 contains three counters which have fixed uses. All registers are in the core well and clocked by a 14.31818 MHz clock. 11.1.1 Counter 0, System Timer This counter functions as the system timer by controlling the state of IRQ0 and is programmed for Mode 3 operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value.
ACPI Devices Table 298. 43h: TCW - Timer Control Word Register Size: 8 bit Default: Undefined Fixed IO Bit Range Default 07 :06 05 :04 03 :01 00 Undef Undef Access WO WO Power Well: Core Address: 43h Acronym CS Description Counter Select: The Counter Selection bits select the counter the control word acts upon as shown below. The Read Back Command is selected when bits[7:6] are both 1.
ACPI Devices Table 299.
ACPI Devices Table 301. 40h, 41h, 42h: Interval Timer Status Byte Format Register Size: 8 bit Default: 0XXXXXXXb Access PCI Configuration Bit Range Default Power Well: Core Offset Start: 40h, 41h, 42h Offset End: B:D:F Access Acronym Description CL Counter State: When set, OUT of the counter is set. When cleared, OUT of the counter is 0.
ACPI Devices 3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the 16- bit counter. 4. Repeat with other counters Only two conventions need to be observed when programming the counters. First, for each counter, the control word must be written before the initial count is written.
ACPI Devices The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch Commands do not affect the programmed mode of the counter in any way.
ACPI Devices Table 303. HPET Registers (Sheet 2 of 2) Start End Symbol 100 107 T0C 108 10F T0CV 120 127 T1C 128 12F T1CV 140 147 T2C 148 14F T2CV Register Timer 0 Config and Capabilities Timer 0 Comparator Value Timer 1 Config and Capabilities Timer 1 Comparator Value Timer 2 Config and Capabilities Timer 2 Comparator Value 11.2.1.1 Offset 000h: GCID – General Capabilities and ID Table 304.
ACPI Devices 11.2.1.3 Offset 020h: GIS – General Interrupt Status Table 306. 020h: GIS – General Interrupt Status Size: 64 bit Access Default: Power Well: Core B:D:F Offset Start: 020h Offset End: 027h PCI Configuration Bit Range Default 63 :03 Access Acronym Description 0 RO RSVD 02 0 RWC T2 Timer 2 Status: Same functionality as T0, for timer 2. Reserved 01 0 RWC T1 Timer 1 Status: Same functionality as T0, for timer 1.
ACPI Devices Table 308. 100h, 120h, 140h: T[0-2]C – Timer [0-2] Config and Capabilities (Sheet 2 of 2) Size: 64 bit Default: Access PCI Configuration Bit Range Default Power Well: Core Offset Start: 100h, 120h, 140h Offset End: 107h, 127h, 147h B:D:F Access Acronym Description 07 0 RO RSVD 06 0 RO/RW TVS Timer Value Set: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1 and 2.
ACPI Devices Table 309. 108h, 128h, 148h: T[0-2]CV – Timer [0-2] Comparator Value Size: 64 bit Default: Access PCI Configuration Bit Range Default 63 :0 See Desc Access Power Well: Core Offset Start: 108h, 128h, 148h Offset End: 10Fh, 12Fh, 14Fh B:D:F Acronym RW Description Timer Compare Value — R/W.
ACPI Devices 11.2.2.2 Periodic Mode – Timer 0 only When set up for periodic mode, when the main counter value matches the value in T0CV, an interrupt is generated (if enabled). Hardware then increases T0CV by the last value written to T0CV. During run-time, T0CV can be read to find out when the next periodic interrupt will be generated. Software is expected to remember the last value written to T0CV.
ACPI Devices 11.2.2.4 Mapping Option #2: Standard Option (GC.LRE cleared) Each timer has its own routing control. The interrupts can be routed to various interrupts in the I/O APIC. TnC.IRC indicates which interrupts are valid options for routing. If a timer is set for edge-triggered mode, the timers should not be shared with any other interrupts. 11.3 8259 Interrupt Controller 11.3.
ACPI Devices 11.3.2 I/O Registers The interrupt controller registers are located at 20h and 21h for the master controller (IRQ0 - 7), and at A0h and A1h for the slave controller (IRQ8 - 13). These registers have multiple functions, depending upon the data written to them. Below is a description of the different register possibilities for each address: Table 313. 8259 I/O Register Mapping Port Aliases Register Name/Function 20h 24h, 28h, 2Ch, 30h, 34h, 38h, 3Ch Master 8259 ICW1 Init.
ACPI Devices Table 314. 20h, A0h: ICW1 – Initialization Command Word 1 (Sheet 2 of 2) Size: 8 bit Default: Access PCI Configuration Bit Range Default Offset Start: 20h, A0h Offset End: B:D:F Access Acronym LTIM 03 Undef WO 02 Undef WO 01 Undef WO SNGL 00 Undef WO IC4 11.3.2.2 Power Well: Core Description Edge/Level Bank Select: Disabled. Replaced by ELCR1 and ELCR2. Reserved, set to 0.
ACPI Devices 11.3.2.3 Offset 21h: MICW3 – Master Initialization Command Word 3 Table 316. 21h: MICW3 – Master Initialization Command Word 3 Size: 8 bit Default: Access PCI Configuration Bit Range Default 07 :03 02 01 :00 Undef Access Power Well: Core Offset Start: 21h Offset End: B:D:F Acronym Description WO These bits must be programmed to zero.
ACPI Devices 11.3.2.6 Offset 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt Mask) Table 319. 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt Mask) Size: 8 bit Default: Access PCI Configuration Bit Range Default 07 :00 00h 11.3.2.7 Access RW Power Well: Core Offset Start: 21h, A1h Offset End: B:D:F Acronym Description IRM Interrupt Request Mask: When a 1 is written to any bit in this register, the corresponding IRQ line is masked.
ACPI Devices Offset 20h, A0h: OCW3 – Operational Control Word 3 Table 321. 20h, A0h: OCW3 – Operational Control Word 3 Size: 8 bit Default: Access PCI Configuration Bit Range Default 07 X Power Well: Core Offset Start: 20h, A0h Offset End: B:D:F Access Acronym Description RO RSVD Reserved. Must be 0.
ACPI Devices 11.3.2.9 Offset 4D1h: ELCR2 – Slave Edge/Level Control Table 323. 4D1h: ELCR2 – Slave Edge/Level Control Size: 8 bit Default: Access PCI Configuration Bit Range Default 07 :06 05 04 :01 00 B:D:F Power Well: Core Offset Start: 4D1h Offset End: Access Acronym Description 0 RW ECL[15:14] Edge Level Control: In edge mode, (bit cleared), the interrupt is recognized by a low to high transition. In level mode (bit set), the interrupt is recognized by a high level.
ACPI Devices Table 324. Content of Interrupt Vector Byte Master, Slave Interrupt Bits [2:0] IRQ7,15 111 IRQ6,14 110 IRQ5,13 101 IRQ4,12 IRQ3,11 11.3.3.3 Bits [7:3] 100 ICW2[7:3] 011 IRQ2,10 010 IRQ1,9 001 IRQ0,8 000 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The 8259 sends INTR active (high) to the CPU if an asserted interrupt is not masked. 3.
ACPI Devices • Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. • The Interrupt Mask Register is cleared. • IRQ7 input is assigned priority 7. • The slave mode address is set to 7. • Special Mask Mode is cleared and Status Read is set to IRR. 11.3.4.2 ICW2 The second write in the sequence, ICW2, is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge.
ACPI Devices Interrupt priorities can be changed in the rotating priority mode. 11.3.6.2 Special Fully Nested Mode This mode will be used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully nested mode will be programmed to the master controller.
ACPI Devices 11.3.6.6 Edge and Level Triggered Mode In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the processor, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1 and ELCR2. If an ELCR bit is ‘0’, an interrupt request will be recognized by a low to high transition on the corresponding IRQ input.
ACPI Devices The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register. Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the Special Mask Mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special Mask Mode is set by OCW3.SSMM and OCW3.SMM set, and cleared when OCW3.SSMM and OCW3.
ACPI Devices 11.4.2 Index Registers The registers listed below can be accessed via the IDX register. When accessing these registers, accesses must be done as DWs, otherwise unspecified behavior will result. Software should not attempt to write to reserved registers. Some reserved registers may return non-zero values when read. Table 326.
ACPI Devices Table 328. 01h: VS – Version Register (Sheet 2 of 2) Size: 32 bit Default: Access PCI Configuration Bit Range Default Offset Start: 01h Offset End: 01h B:D:F Access Acronym 14 :08 0 RO RSVD 07 :00 20h RO VS 11.4.2.3 Power Well: Core Description Reserved Version: Identifies the implementation version as IOxAPIC.
ACPI Devices 11.4.3 Unsupported Modes These delivery modes are not supported for the following reasons: • NMI/INIT: This cannot be delivered while the CPU is in the Stop Grant state. In addition, this is a break event for power management. • SMI: There is no way to block the delivery of the SMI#, except through BIOS. • Virtual Wire Mode B: The processor does not support the INTR of the 8259 routed to the I/OxAPIC pin 0. 11.4.4 Interrupt Delivery 11.4.4.
ACPI Devices 11.4.4.5 Interrupt Delivery Data Value Table 331. Interrupt Delivery Data Value Bit 31:16 0000h 15 Trigger Mode: RTE[x].TM 14 Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit is always set to ‘1’. 13:12 11 11.4.5 Description 00 Destination Mode: RTE[x].DSM 10:08 Delivery Mode: RTE[x].DLM 07:00 Vector: RTE[x].
ACPI Devices • Start Frame: SERIRQ line driven low by the interrupt controller to indicate the start of IRQ transmission • Data Frames: IRQ information transmitted by peripherals. The interrupt controller supports 21 data frames. • Stop Frame: SERIRQ line driven low by the interrupt controller to indicate end of transmission and next mode of operation. 11.5.
ACPI Devices 11.5.5 Serial Interrupts Not Supported There are 4 interrupts on the serial stream which are not supported by the interrupt controller. These interrupts are generated internally, and are not sharable with other devices within the system. These interrupts are: • IRQ0: Heartbeat interrupt generated off of the internal 8254 counter 0. • IRQ8#: RTC interrupt can only be generated internally. • IRQ13: This interrupt (floating point error) is not supported in the processor.
ACPI Devices 11.6 Real Time Clock 11.6.1 Overview The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device. Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 μs to 500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week, month, and year are counted. The hour is represented in twelve or twenty-four hour format, and data can be represented in BCD or binary format.
ACPI Devices Table 335. RTC Indexed Registers Start 11.6.3.
ACPI Devices Table 336. 0Ah: Register A (Sheet 2 of 2) Size: 8 bit Access Default: Power Well: RTC B:D:F Offset Start: 0Ah Offset End: 0Ah PCI Configuration Bit Range Default Access Acronym Description Rate Select: Selects one of 13 taps of the 15 stage divider chain. The selected tap can generate a periodic interrupt if B.PIE bit is set. Otherwise this tap will set C.PF. 03 :00 Undef 11.6.3.2 RW RS Bits Function Bits Function 0h 1h Interrupt never toggles 8h 3.90625 ms 3.
ACPI Devices Table 338. 0Ch: Register C - Flag Register Size: 8 bit Access Power Well: RTC B:D:F Offset Start: 0Ch Offset End: 0Ch PCI Configuration Bit Range Default 07 Default: Access Acronym 0 RO IRQF Description Interrupt Request Flag: This bit is an AND of the flag with its corresponding interrupt enable in register B, and causes the RTC Interrupt to be asserted. 06 0 RO PF Periodic Interrupt Flag: Set when the tap as specified by A.RS is one.
ACPI Devices 11.7 General Purpose I/O 11.7.1 Core Well GPIO I/O Registers The control for the general purpose I/O signals is handled through an independent 64byte I/O space. The base offset for this space is selected by the GPIO_BAR register in D31:F0 config space. Note: the Core Well GPIO registers are mapped to the “GPIO” pins and the resume well are mapped to the GPIOSUS[n] pins. Table 340.
ACPI Devices 11.7.1.2 Offset 04h: CGIO – Core Well GPIO Input/Output Select Table 342. 04h: CGIO – Core Well GPIO Input/Output Select Size: 32 bit Default: 0000001Fh Access PCI Configuration B:D:F 0:31:0 Memory Mapped IO Bit Range Default BAR: GPIO_BAR (IO) Access Acronym 31 :05 0 RO RSVD 04 :00 1Fh RW IO Power Well: Core Offset Start: 04h Offset End: 07h Offset: Description Reserved Input/Output: When set, the GPIO signal (if enabled) is programmed as an input.
ACPI Devices 11.7.1.5 Offset 10h: CGTNE – Core Well GPIO Trigger Negative Edge Enable Table 345. 10h: CGTNE – Core Well GPIO Trigger Negative Edge Enable Size: 32 bit Default: 00000000h Access PCI Configuration B:D:F 0:31:0 Memory Mapped IO Bit Range Default Power Well: Core Offset Start: 10h Offset End: 13h BAR: GPIO_BAR (IO) Access Acronym 31 :05 0 RO RSVD 04 :00 0 RW TE Offset: Description Reserved Trigger Enable: When set, the corresponding GPIO, if enabled as input via GIO.
ACPI Devices 11.7.1.8 Offset 1Ch: CGTS – Core Well GPIO Trigger Status Table 348. 1Ch: CGTS – Core Well GPIO Trigger Status Size: 32 bit Default: 00000000h Access PCI Configuration 31 :05 04 :00 Acronym RO RSVD 0 11.7.2 BAR: GPIO_BAR (IO) Access 0 RWC Offset Start: 1Ch Offset End: 1Fh B:D:F 0:31:0 Memory Mapped IO Bit Range Default Power Well: Core Offset: Description Reserved Trigger Status: When set, the corresponding GPIO, if enabled as input via GIO.IO[n], triggered an SMI#/SCI.
ACPI Devices Table 350. 20h: RGEN – Resume Well GPIO Enable (Sheet 2 of 2) Size: 32 bit Default: 000001FFh Access PCI Configuration B:D:F 0:31:0 Memory Mapped IO Bit Range Default 08 :00 1FFh Power Well: Resume Offset Start: 20h Offset End: 23h BAR: GPIO_BAR (IO) Access Acronym RW EN Offset: Description Enable: When set, enables the pin as a GPIO. When cleared, the pin, if muxed, returns to its normal use. This field has no effect on unmuxed GPIOs. 11.7.2.
ACPI Devices 11.7.2.4 Offset 2Ch: RGTPE – Resume Well GPIO Trigger Positive Edge Enable Table 353.
ACPI Devices 11.7.2.7 Offset 38h: RGSMI – Resume Well GPIO SMI Enable Table 356. 38h: RGSMI – Resume Well GPIO SMI Enable Size: 32 bit Default: 00000000h Access PCI Configuration B:D:F 0:31:0 Memory Mapped IO Bit Range Default BAR: GPIO_BAR (IO) Access Acronym 31 :09 0 RO RSVD 08 :00 00 RW EN Power Well: Resume Offset Start: 38h Offset End: 3Bh Offset: Description Reserved Enable: When set, when RGTS.TS[n] is set, the ACPI SMIS.GPIO bit will be set. 11.7.2.
ACPI Devices 11.8 SMBus Controller 11.8.1 Overview The processor provides an SMBus 1.0-compliant host controller. The host controller provides a mechanism for the CPU to initiate communications with SMB peripherals (slaves). 11.8.2 I/O Registers Table 358.
ACPI Devices Table 359. 00h: HCTL - Host Control Register (Sheet 2 of 2) Size: 8 bit Default: 00h Access PCI Configuration Bit Range Default Access Power Well: Core Offset Start: 00h Offset End: 00h B:D:F Acronym Description Command: Indicates the command the processor is to perform. If enabled, the processor will generate an interrupt or SMI# when the command has completed. If a reserved command is issued, the processor will set HSTS.DE and perform no command, and will not operate until HSTS.
ACPI Devices 11.8.2.3 Offset 02h: HCLK – Host Clock Divider Table 361. 02h: HCLK – Host Clock Divider Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default Access Power Well: Core Offset Start: 02h Offset End: 03h B:D:F Acronym Description Divider: This controls how many legacy backbone clocks should be counted for the generation of SMBCLK. Recommended values are listed below: 15 :00 0 11.8.2.
ACPI Devices 11.8.2.6 Offset 06h: HD0 - Host Data 0 This field is transmitted in the DATA0 field of an SMBus cycle. For block writes, this register reflects the number of bytes to transfer. This register should be programmed to a value between 1h (1 bytes) and 20h (32 bytes) for block counts. A count of 00h or above 20h will result in no transfer and HSTS.CS will be cleared, indicating a failure. Table 364.
ACPI Devices The host controller supports eight command protocols of the SMB interface (see the System Management Bus Specification, Version 1.0.): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process call, Block Read, Block Write and Block write-block read process call. The host controller requires the various data and command fields be setup for the type of command to be sent. When software sets HCTL.
ACPI Devices 11.8.5.2 Bus Time Out If there is an error in the transaction, such that a device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. The processor will discard the cycle, and set HSTS.DE. The time out minimum is 25 ms. The time-out counter inside the processor will start when the first bit of data is transferred by the processor. 11.8.6 SMI# The system can be set up to generate SMI# by setting HCTL.SE. 11.
ACPI Devices Table 369. GPIO Boot Source Selection GPIO[0] 11.9.4 Description 1 Boot from SPI 0 Boot from LPC SPI Protocol Communication on the SPI bus is done with a Master – Slave protocol. Typical bus topologies call for a single SPI Master with a single SPI Slave. The SPI interface consists of a four wire interface: clock (CLK), master data out (Master Out Slave In (MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select (CS#). 11.9.4.
ACPI Devices The processor only supports Mode 0. Commands, Addresses and Data are shifted most significant bit (MSB) first. For the 24bit address, this means bit 23 is shifted first while bit 0 is shifted last. However, for data bursts, bytes are shifted out from least significant byte to most significant byte, where each byte is shifted (MSB to LSB). 11.9.4.1.1 Addressing A Slave is targeted for a cycle when it’s SPI_CS# pin is asserted.
ACPI Devices Table 370. Instructions (Sheet 2 of 2) Instruction ST* M25P80 (8 Mb) ST* M45P80 (8 Mb) NexFlash* NX25P SST* 25V040 (4 Mb) SST* 25VF080 (8 Mb) 06 06 06 06 - 0A - - 0B 0B 0B - - - - 50 256B Erase - DB - - 4 kByte Erase - - - 20 64 kB Erase D8 D8 D8 52 Chip Erase C7 - C7 60 Write Enable Page Write Fast Read (1) Ena Write Status Auto Add Inc (2) - - - AF Power Down/Up B9 / AB B9 / AB B9 - - 9F 90 AB or 90 Read ID Note: 1.
ACPI Devices Table 372.
ACPI Devices 11.9.5.3 Offset 02h: SPIC – SPI Control Table 374. 02h: SPIC - SPI Control Size: 16 bit Default: 2005h Access PCI Configuration B:D:F 0:31:0 Offset Start: 3022h Offset End: 3023h BAR: RCBA Offset: Memory Mapped IO Bit Range Default Power Well: Core Access Acronym Description SPI SMI# Enable: When set to 1, the SPI asserts an SMI# request whenever the Cycle Done Status bit is 1.
ACPI Devices 11.9.5.4 Offset 04h: SPIA – SPI Address Table 375. 04h: SPIA - SPI Address Size: 32 bit Default: 00XXXXXh Access PCI Configuration B:D:F 0:31:0 Offset Start: 3024h Offset End: 3027h BAR: RCBA Offset: Memory Mapped IO Bit Range Default Access Acronym 31 :24 0 RV RSVD 23 :00 0 RW SCA Description Reserved SPI Cycle Address: This field is shifted out as the SPI Address (MSB first). 11.9.5.5 Offset 08h: SPID0 – SPI Data 0 Table 376.
ACPI Devices 11.9.5.6 Offset 10h, 18h, 20h, 28h, 30h, 38h, 40h: SPID[0-6] – SPI Data N Table 377. 10h, 18h, 20h, 28h, 30h, 38h, 40h: SPID[0-6] - SPI Data [0-6] Size: 64 bit Default: 00000000h Access PCI Configuration B:D:F 0:31:0 Memory Mapped IO Bit Range Default 63 :00 0 11.9.5.7 BAR: RCBA Access Acronym RW0 SCD Power Well: Core Offset Start: 3030h at 4h Offset End: 306Ch at 4h Offset: Description SPI Cycle Data N (SCD[N]): Similar definition as SPI Cycle Data 0.
ACPI Devices Table 379. 54h: PREOP - Prefix Opcode Configuration Size: 16 bit Default: 0004h Access PCI Configuration B:D:F 0:31:0 Offset Start: 3074h Offset End: 3075h BAR: RCBA Offset: Memory Mapped IO Bit Range Default Access Acronym Description 0 RWS PO1 Prefix Opcode 1: Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence.
ACPI Devices It is recommended that BIOS avoid programming Write Enable opcodes in this menu. Malicious software could then perform writes and erases to the SPI flash without using the atomic cycle mechanism. Write Enable opcodes should only be programmed in the Offset 54h: PREOP – Prefix Opcode Configuration. Table 381.
ACPI Devices 11.9.5.12 Running SPI Cycles from the Host 11.9.5.12.1 Memory Reads Memory Reads to the BIOS Range result in a READ command (03h) with the lower 3 bytes of the address delivered in the SPI cycle. By sending the entire 24 bits of address out to the SPI interface unchanged, the processor hardware can support various flash memory sizes without having straps or automatic detection algorithms in hardware.
ACPI Devices Note that, although the SPI interface may “burst ahead” for up to 64 bytes, the Host Interface may still have to wait for prefetched data to arrive from the flash before generating the completion back to the processor. The round trip delay for the platform to complete one DWord and run the host read for the next sequential DWord can be shorter than the SPI time to receive another 32 bits.
ACPI Devices 11.9.5.13 Generic Programmed Commands All commands other than the standard (memory) reads must be programmed by the BIOS in the SPI Control, address, data, and opcode configuration registers in Section 11.9.5.1. The opcode type in Offset 56h: OPTYPE – Opcode Type Configuration and data byte count fields in Offset 54h: PREOP – Prefix Opcode Configuration determine how many clocks to run before deasserting the chip enable.
ACPI Devices Table 384. Flash Protection Summary Mechanism Accesses Blocked Range Specific Reset-Override or SMI#Override Equivalent Function on FWH BIOS Range Write Protection Writes Yes Reset Override FWH Sector Protection SMI#-Based Global Write Protection Writes No SMI# Override Same as Write Protect in previous chipset for FWH The processor provides these protections in hardware.
ACPI Devices Note that once BIOS has locked down the BIOS BAR, this mechanism remains in place until the next system reset. There is one exception where processor-initiated reads may access data below the BIOS Base Address. If a programmed read (or Direct Memory Read) is initiated at the top of flash such that the length exceeds the top of flash memory, the read burst may wrap around to location 0. 11.9.5.14.
ACPI Devices Table 385. Flash Erase Time Device Erase Time (max) Description PMC* PM25LV 100 ms Same for block or sector Atmel* AT25F 1.1 s SST* SST25VF 25, 25, 100 ms Sector, block, chip NexFlash* NX25P 2, 3/5 s Sector, chip 2 mb/4 mb ST* M25P80 3s Sector The Write process is executed to write bytes to the Flash device. The atomic instructions that make up the Write process include a Write enable instruction, a Write (or Program) instruction and finally a status poll.
ACPI Devices The following table shows the different device write times for doing a 512 kB sector write. Table 386. 11.9.7.3 Flash Write Time Device Write Time Worst Case/ Typical PMC* PM25LV 41/8 s Atmel* AT25F 1/.7 s SST* SST25VF ~13 s NexFlash* NX25P 41/16 s ST* M25P80 4/11.71 s ST* M45P80 41/10 s Description Two options for byte writes with this device: byte write and byte write with auto address increment. However, only the standard byte write is supported by the processor.
ACPI Devices 9. Lock down the SPI registers, Offset 00h: SPIS – SPI Status bit 15 10. Set Up SMI based write protection as needed (same as FWH) 11.10 Watchdog Timer 11.10.1 Overview This Watchdog timer provides a resolution that ranges from 1 µs to 10 minutes. The timer uses a 35-bit down-counter. After the interrupt is generated the WDT loads the value from the Preload register into the WDT’s 35-bit Down-Counter and starts counting down.
ACPI Devices Table 387.
ACPI Devices 11.10.3.2 Offset 01h: PV1R1 - Preload Value 1 Register 1 Table 389. 01h: PV1R1 - Preload Value 1 Register 1 Size: 8 bit Default: FFh Access PCI Configuration IA F Bit Range Default 07 : 00 Offset Start: 01h Offset End: 01h B:D:F Base Address: Base (IO) Access FFh Power Well: Core RW Acronym PLOAD1_15_8 Offset: 01h Description Preload_Value_1 [15:8]: This register is used to hold the bits 8 through 15 of the preload value 1 for the WDT Timer.
ACPI Devices 11.10.3.4 Offset 04h: PV2R0 - Preload Value 2 Register 0 Table 391. 04h: PV2R0 - Preload Value 2 Register 0 Size: 8 bit Default: FFh Access PCI Configuration IA F Bit Range Default 07 : 00 Offset Start: 04h Offset End: 04h B:D:F Base Address: Base (IO) Access FFh Power Well: Core RW Acronym Offset: 04h Description Preload_Value_2 [7:0]: This register is used to hold the bits 0 through 7 of the preload value 2 for the WDT Timer.
ACPI Devices Table 393. 06h: PV2R2 - Preload Value 2 Register 2 (Sheet 2 of 2) Size: 8 bit Default: 0Fh Access PCI Configuration IA F Bit Range Default 03 : 00 Offset Start: 06h Offset End: 06h B:D:F Base Address: Base (IO) Access Fh RW Acronym Preload_Value_2 [19:16]: This register is used to hold the bits 16 through 19 of the preload value 2 for the WDT Timer. The Value in the Preload Register is automatically transferred into the 35-bit down counter.
ACPI Devices 11.10.3.9 Offset 10h: WDTCR - WDT Configuration Register Table 396.
ACPI Devices 11.10.3.11 Offset 15h: DCR1 - Down Counter Register 1 Table 398. 15h: DCR1 - Down Counter Register 1 Size: 8 bit Default: 00h Access PCI Configuration IA F Bit Range Default 07 : 00 Offset Start: 15h Offset End: 15h B:D:F Base Address: Base (IO) Access 00h Power Well: Core RO Offset: 15h Acronym Description DCNT_15_8 Down-Counter [15:8]: The Down-Counter register holds the bits 8 through 15 of upper 20-bits of the 35-bit down counter that is continuously decremented.
ACPI Devices Table 400. 18h: WDTLR - WDT Lock Register (Sheet 2 of 2) Size: 8 bit Default: 00h Access PCI Configuration IA F Bit Range Default 01 00 0h 0h Power Well: Core Offset Start: 18h Offset End: 18h B:D:F Base Address: Base (IO) Access RW RWL Acronym Offset: 18h Description Watchdog Timer Enable: The following bit enables or disables the WDT. 0 = Disabled (Default) 1 = Enabled Note: This bit cannot be modified if WDT_LOCK has been set.
ACPI Devices 11.10.4.3 Reload Sequence To keep the timer from causing an interrupt or driving GPIO[4], the timer must be updated periodically. Other timers refer to “updating the timer” as “kicking the timer”. The frequency of updates required is dependent on the value of the Preload values. To update the timer the Register Unlocking Sequence must be performed followed by writing a ‘1’ to bit 8 at offset BAR1 + 0Ch within the watchdog timer memory mapped space.
ACPI Devices Intel® Atom™ Processor E6xx Series Datasheet 272
Absolute Maximum Ratings 12.0 Absolute Maximum Ratings Table 401 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected.
Absolute Maximum Ratings 12.1 Absolute Maximum Rating Table 401. Absolute Maximum Ratings Symbol Parameter Min Max TSTORAGE The non-operating device storage temperature. -25 125 TSUSTAINED The ambient storage temperature limit (in shipping media) for a sustained period of time. -5 40 STORAGE RHSUSTAINED StORAGE The maximum device storage relative humidity for a sustained period of time.
DC Characteristics 13.0 DC Characteristics 13.1 Signal Groups The signal description includes the type of buffer used for the particular signal. Please refer to the Chapter 2.0 for signals detail. Table 402. Memory Controller Buffer Types Buffer Type Description AGTL+ Assisted Gunning Transceiver Logic Plus. Open Drain interface signals that require termination. Refer to the AGTL+ I/O Specification for complete details. CMOS, CMOS Open Drain 1.
DC Characteristics 13.2 Power and Current Characteristics Table 403. Thermal Design Power Symbol Parameter Range Unit Notes TDP_UL Thermal Design Power (Ultra-Low SKU) (at 1.05-V Core Voltage) 3.3 W 1 TDP_E Thermal Design Power (Entry SKU) (at 1.05-V Core Voltage) 3.6 W 1 TDP_M Thermal Design Power (Mainstream SKU) (at 1.05-V Core Voltage) 3.6 W 1 TDP_P Thermal Design Power (Premium SKU) (at 1.05-V Core Voltage) 4.5 W 1 Notes: 1.
DC Characteristics 13.3 General DC Characteristics Table 405. Operating Condition Power Supply and Reference DC Characteristics Symbol Parameter Min. Typ. Max. Unit Notes - 1.15 V 1,2,3 - AVID V 1,2,3 V 1,3 VCC HFM VCC @ Highest Frequency Mode AVID VCC LFM VCC @ Lowest Frequency Mode 0.75 VCC C6 VID VCC @ C6 CPU State 0.3 VCC BOOT Default VCC for initial power - VCC LFM - V 1,2,3 VNN BOOT Default VNN for initial power - VNN - V 1,2,3 VNN VNN Supply Voltage 0.
DC Characteristics . Table 406. Active Signal DC Characteristics (Sheet 1 of 3) Symbol Parameter Min Nom Max Unit 0.2 x VCCD V Notes CMOS1.05 VIL Input Low Voltage –0.1 0.0 VIH Input High Voltage 0.8 x VCCD VCCD VCCD + 0.1 V VOL Output Low Voltage -0.1 0 0.1 x VCCD V VCCD VCCD + 0.1 V 4.1 mA VOH Output High Voltage 0.9 x VCCD IOL Output Low Current 1.5 IOH Output High Current 1.5 IIL Input Low Current Cpad Pad Capacitance 0.95 4.1 mA ± 100 µA 1.2 1.
DC Characteristics Table 406. Active Signal DC Characteristics (Sheet 2 of 3) Symbol Parameter Min Nom Max Unit Notes System Memory (CMOS1.8) VIL Input Low Voltage -0.4 (VCC180/2) – 0.125 V VIH Input High Voltage (VCC180/2) + 0.125 1.9 V VOL Output Low Voltage (VCC180/2) – 0.250 V VOH Output High Voltage (VCC180/2) + 0.
DC Characteristics Table 406. Active Signal DC Characteristics (Sheet 3 of 3) Symbol Parameter VIH Maximum input voltage VIL Minimum input voltage Min Nom Max 1.15 -0.3 Unit Notes V 7, 9, 12 V 7, 9, 13 RTCRST#,PWROK,RSMRST# 2.0 VIH Input high voltage 2.17 VCC33RTC + 0.1 V 0.78 VIL Input low voltage -0.5 V 0.68 B1 Stepping B0 Stepping B1 Stepping B0 Stepping RTCX1 VIH Input high voltage 0.5 1.2 V VIL Input low voltage -0.5 0.1 V Notes: 1. VOL < VPAD < VTT 2.
Ballout and Package Information 14.0 Ballout and Package Information The Intel® Atom™ Processor E6xx Series comes in an 22 mm x 22 mm Flip-Chip Ball Grid Array (FCBGA) package and consists of a silicon die mounted face down on an organic substrate populated with 676 solder balls on the bottom side. Capacitors may be placed in the area surrounding the die.
Ballout and Package Information 14.1 Package Diagrams Figure 10.
Ballout and Package Information Figure 11.
Ballout and Package Information 14.2 Ballout Definition and Signal Locations Figure 12 provides the ballout as viewed from the top of the package. Table 407 lists the ballout alphabetically by signal name. Figure 12.
Ballout and Package Information Figure 13.
Ballout and Package Information Figure 14.
Ballout and Package Information Figure 15.
Ballout and Package Information Figure 16.
Ballout and Package Information Figure 17.
Ballout and Package Information Table 407. Table 407.
Ballout and Package Information Table 407.
Ballout and Package Information Table 407. Pin List Pin Name VCC180 VCC180 VCC180 VCC180SR VCC33RTC VCCA VCCA VCCA VCCA_PEG VCCA_PEG VCCA_PEG VCCA_PEG VCCA_PEG VCCA_PEG VCCA_PEG VCCA180 VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD_DPL VCCD180 VCCDSENSE VCCDSUS VCCF VCCFHV VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP33 VCCP33 VCCP33 VCCP33SUS VCCPA VCCPA VCCPDDR Table 407.
Ballout and Package Information Table 407. Pin List Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Table 407.
Ballout and Package Information Table 407. Pin List Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Table 407.
