Datasheet

Interfaces
34 Datasheet
When eDP is enabled, the lower logical lanes are still available for standard PCIe
devices, using the PEG 0 controller. PEG 0 is limited to x1. The board manufacture
chooses whether to use eDP and whether to use lane numbering reversal.
The eDP interface supports link-speeds of 1.62 Gbps and 2.7 Gbps on 1, 2 or 4 data
lanes. The eDP and PCI Express x1 may be supported concurrently. eDP interface may
support -0.5% SSC and non-SSC clock settings.
2.4.3 Intel Flexible Display Interface
The Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying display
traffic from the integrated graphics controller to the PCH display I/Os. Intel FDI
supports two independent channels; one for pipe A and one for pipe B.
 Each channel has four transmit (Tx) differential pairs used for transporting pixel
and framing data from the display engine.
 Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS
signaling).
 One display interrupt line input (1-V CMOS signaling).
 Intel FDI may dynamically scalable down to 2X or 1X based on actual display
bandwidth requirements.
 Common 100-MHz reference clock is sent to both processor and PCH.
 Each channel transports at a rate of 2.7 Gbps.
 PCH supports end-to-end lane reversal across both channels (no reversal support
required)
2.5 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (processor) and a PECI master, usually the PCH. The processor implements
a PECI interface to:
eDP_TX[0] PEG_TX[15] PEG_TX[0]
eDP_TX#[0] PEG_TX#[15] PEG_TX#[0]
eDP_TX[1] PEG_TX[14] PEG_TX[1]
eDP_TX#[1] PEG_TX#[14] PEG_TX#[1]
eDP_TX[2] PEG_TX[13] PEG_TX[2]
eDP_TX#[2] PEG_TX#[13] PEG_TX#[2]
eDP_TX[3] PEG_TX[12] PEG_TX[3]
eDP_TX#[3] PEG_TX#[12] PEG_TX#[3]
Table 2-3. eDP/PEG Ball Mapping
eDP Signal PEG Signal Lane Reversal