Datasheet

Datasheet 15
Features Summary
1.3.6 Embedded DisplayPort* (eDP*)
 Shared with PCI Express Graphics port
 Shared on upper four logical lanes, after any lane reversal
 eDP[3:0] map to PEG[12:15] (non-reversed)
 eDP[3:0] map to PEG[3:0] (reversed)
 Concurrent eDP and PEG x1 supported
1.3.7 Intel® Flexible Display Interface (Intel® FDI)
 Carries display traffic from the integrated graphics controller in the processor to the
legacy display connectors in the PCH.
 Based on DisplayPort standard.
 Two independent links - one for each display pipe.
 Four unidirectional downstream differential transmitter pairs:
 Scalable down to 3X, 2X, or 1X based on actual display bandwidth requirements
 Fixed frequency 2.7 GT/s data rate
 Two sideband signals for Display synchronization:
 FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)
 One Interrupt signal used for various interrupts from the PCH:
 FDI_INT signal shared by both Intel FDI Links
 PCH supports end-to-end lane reversal across both links.
1.4 Power Management Support
1.4.1 Processor Core
 Full support of ACPI C-states as implemented by the following processor C-states:
 Ultra low voltage supports C0, C1, C1E, C3, Deep Power Down Technology (code
named C6)
 Standard voltage supports C0, C1, C1E, C3
 Enhanced Intel SpeedStep® Technology
1.4.2 System
 S0, S3, S4, S5