Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Datasheet —on 65 nm Process in the 775-land LGA Package supporting Intel® 64 architecture and Intel® Virtualization Technology± August 2007 Document Number: 315592-005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Terminology ............................................................................ 10 1.2 References .......................................................................................................
5.3 5.2.5 THERMTRIP# Signal ................................................................................79 Platform Environment Control Interface (PECI) ......................................................80 5.3.1 Introduction ...........................................................................................80 5.3.1.1 TCONTROL and TCC Activation on PECI-Based Systems.....................80 5.3.2 PECI Specifications .............................................................................
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Datasheet VCC Static and Transient Tolerance ............................................................................. 20 VCC Overshoot Example Waveform ............................................................................. 21 Differential Clock Waveform ...................................................................................... 29 Differential Clock Crosspoint Specification .....................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 6 References ..............................................................................................................11 Voltage Identification Definition ..................................................................................15 Absolute Maximum and Minimum Ratings ....................................................................17 Voltage and Current Specifications..........................
Revision History Revision Number -001 -002 -003 -003 Description • Initial release Date November 2006 ® • • • • Added specifications for the Intel Core™2 Quad Processor Q6600 Updated Table 8, “Signal Characteristics”. Updated VTT_SEL description in Table 24. Updated Table 29, “Fan Heatsink Power and Signal Specifications”.
Intel® Core™2 Extreme Quad-Core Processor QX6000 and Intel® Core™2 Quad Processor Q6000 Sequence Features • Available at 3.00 GHz (Intel® Core™2 Extreme Quad-Core Processor QX6850 only) • Available at 2.66 GHz (Intel® Core™2 Extreme Quad-Core Processor QX6700 and Intel® Core™2 Quad Processor Q6700 only) • Available at 2.40 GHz (Intel® Core™2 Quad Processor Q6600 only) • Available at 2.
Introduction 1 Introduction The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence are the first desktop quad-core processors that combine the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, and gaming experiences. They are 64-bit processors that maintain compatibility with IA-32 software.
Introduction “Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O. 1.1.1 Processor Terminology Commonly used terms are explained here for clarification: • Intel® Core™2 Extreme quad-core processor QX6000 sequence — Quad core processor in the FC-LGA6 package with a 2x4 MB L2 cache.
Introduction • Enhanced Intel Technology SpeedStep® Technology — Enhanced Intel Technology SpeedStep® Technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.9250 0 1 1 0 0 0 1.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.5 Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.5.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol VID Range Parameter VID Processor Number VCC 3.00 GHz QX6800 2.93 GHz QX6700 2.66 GHz Q6700 2.66 GHz Q6600 2.40 GHz VCC_BOOT Default VCC voltage for initial power up VCCPLL PLL VCC ICC VTT VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT Max Unit 0.8500 — 1.5 V 3 Refer to Table 5 and Figure 1 V 4, 5, 6 V — 1.10 — - 5% 1.
Electrical Specifications 8. ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details. 9. These Processors have CPUID = 06FBh 10. The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the assertion of PROCHOT#) is the same as the maximum ICC for the processor. 11. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land. 12.
Electrical Specifications Figure 1. VCC Static and Transient Tolerance Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 Vcc Maximum VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 Vcc [V] VID - 0.100 Vcc Typical VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 Vcc Minimum VID - 0.163 VID - 0.175 VID - 0.188 VID - 0.200 VID - 0.213 VID - 0.225 NOTES: 1.
Electrical Specifications 2.5.3 VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID).
Electrical Specifications 2.6 Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary.
Electrical Specifications Table 7.
Electrical Specifications 2.6.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/ deasserted for at least four BCLKs for the processor to recognize the proper signal state. See Section 2.6.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 2.6.
Electrical Specifications Table 12. CMOS Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 3, 4, 5 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 3, 5,6 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications.
Electrical Specifications 2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications 2.7.4 BCLK[1:0] Specifications Table 17. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.30 N/A N/A V 3 2 VH Input High Voltage N/A N/A 1.15 V 3 2 0.300 N/A 0.550 V 3, 4 3, 4, 5 VCROSS(abs) Absolute Crossing Point Range of Crossing Points N/A N/A 0.140 V 3, 4 - VOS Overshoot N/A N/A 1.4 V 3 6 VUS Undershoot -0.
Electrical Specifications Table 19. FSB Differential Clock Specifications (1333 MHz FSB) Min Nom Max Unit Figure Notes1 BCLK[1:0] Frequency 331.635 — 333.364 MHz - 2 T1: BCLK[1:0] Period 2.99972 — 3.01536 ns 3 3 — — 150 ps 3 4, 5 T5: BCLK[1:0] Rise and Fall Slew Rate 2.5 — 8 V/nS 5 6 T6: Slew Rate Matching N/A N/A 20 % T# Parameter T2: BCLK[1:0] Period Stability 7 NOTES: 1.
Electrical Specifications Figure 4. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 300 + 0.5 (VHavg - 700) 350 300 250 300 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 5. Differential Measurements Sl ew_ ris e Slew _fal l +1 50 mV +150 mV 0.0 V V_swin g 0.
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 7.
Package Mechanical Specifications Figure 8.
Package Mechanical Specifications Figure 9.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 7 and Figure 8 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications Figure 11. Processor Top-Side Markings Example for 1333 MHz Processors INTEL M ©'05 QX6850 INTEL® CORE™2 EXTREME SLxxx [COO] 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 12.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 13 and Figure 14. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 13.
Land Listing and Signal Descriptions Figure 14.
Land Listing and Signal Descriptions Table 23. Land Name 42 Alphabetical Land Assignments Land Signal # Buffer Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Land Signal # Buffer Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 44 Alphabetical Land Assignments Land Signal # Buffer Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal # Buffer Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 46 Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 48 Alphabetical Land Assignments Land Signal # Buffer Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 50 Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 23.
Land Listing and Signal Descriptions Table 24. Land # 52 Numerical Land Assignment Land Name Signal Buffer Type A2 VSS Power/Other A3 RS2# Common Clock A4 D02# A5 D04# Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type C20 DBI3# C21 D58# C22 VSS Power/Other C23 VCCIOPLL C24 VSS C25 C26 Table 24.
Land Listing and Signal Descriptions Table 24. 54 Numerical Land Assignment Land # Land Name F11 D23# F12 D24# Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Land # 56 Numerical Land Assignment Land Name Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type U28 VCC U29 U30 Table 24.
Land Listing and Signal Descriptions Table 24. 58 Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AF12 VCC Table 24.
Land Listing and Signal Descriptions Table 24. Land # 60 Numerical Land Assignment Land Name Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AL18 VCC AL19 AL20 Table 24.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 2 of 9) Name BPM[5:0]# BPMb[3:0]# Type Input/ Output Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# and BPMb[3:0]# should connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 4 of 9) Name DEFER# DRDY# Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 5 of 9) Name HIT# HITM# IERR# Type Input/ Output Input/ Output Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 6 of 9) Name Type Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. LOCK# Input/ Output PECI Input/ Output PECI is a proprietary one-wire bus interface. See Section 5.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 7 of 9) Name Type Description RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents. SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 8 of 9) Name Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 9 of 9) Name Type Description VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to VSS. VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA Input VSSA is the isolated ground for internal PLLs.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 27. Figure 15. Thermal Profile for 130 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 42.4 34 48.2 68 54.0 102 59.7 2 42.7 36 48.5 70 54.3 104 60.1 4 43.1 38 48.9 72 54.6 106 60.4 6 43.4 40 49.2 74 55.0 108 60.8 8 43.8 42 49.5 76 55.3 110 61.1 10 44.1 44 49.9 78 57.7 112 61.4 12 44.4 46 50.2 80 56.0 114 61.8 14 44.
Thermal Specifications and Design Considerations Table 28. Figure 16. Thermal Profile for 105 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.3 28 48.3 56 53.4 84 58.4 2 43.7 30 48.7 58 53.8 86 58.8 4 44.0 32 49.1 60 54.1 88 59.1 6 44.4 34 49.4 62 54.5 90 59.5 8 44.7 36 49.8 64 54.9 92 59.9 10 45.1 38 50.1 66 55.2 94 60.3 12 45.5 40 50.5 68 55.4 96 60.6 14 45.
Thermal Specifications and Design Considerations Table 29. Figure 17. Datasheet Thermal Profile 95 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 44.4 28 52.2 56 60.1 84 67.9 2 45.0 30 52.8 58 60.6 86 68.5 4 45.5 32 53.4 60 61.2 88 69.0 6 46.1 34 53.9 62 61.8 90 69.6 8 46.6 36 54.5 64 62.3 92 70.2 10 47.2 38 55.0 66 62.9 94 70.7 12 47.8 40 55.6 68 63.4 95 71.0 14 48.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 18 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Figure 18.
Thermal Specifications and Design Considerations under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 19. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire; thus, alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps).
Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The socket 0 PECI register resides at address 30h and socket 1 resides at 31h. Note that each address also supports two domains (Domain 0 and Domain 1). For more information on PECI domains, refer to the Platform Environment Control Interface Specification. 5.3.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification.
Thermal Specifications and Design Considerations 82 Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 31. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 21.
Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
Features 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Extended HALT Snoop State. 6.2.4.
Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 22 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 24. Space Requirements for the Boxed Processor (Top View) NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 25.
Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. Refer to Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications Figure 26. Boxed Processor Fan Heatsink Power Cable Connector Description Pin 1 2 3 4 Signal GND +12 V SENSE CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. 1 2 3 4 Table 32. Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 11.4 12 12.
Boxed Processor Specifications Figure 27. Baseboard Power Header Placement Relative to Processor Socket 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View) Figure 29.
Boxed Processor Specifications 7.3.2 Fan Speed Control Operation (Intel® Core™2 Extreme processors only) The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed. The fan speed can be controlled by hardware and software from the motherboard. This is accomplished by varying the duty cycle of the Control signal on the 4th pin (see Table 32).
Boxed Processor Specifications Figure 30. Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise Level Increasing Fan Speed & Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) Table 33. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed.
Boxed Processor Specifications If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet.
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 98 Datasheet
