Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 98
Documentation Changes
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask
Instruction Operand Encoding
...
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask
Instruction Operand Encoding
...
MOVNTDQA — Load Double Quadword Non-Temporal Aligned Hint
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 50 /r MOVMSKPD reg,
xmm
AValid Valid Extract 2-bit sign mask from
xmm and store in reg. The
upper bits of r32 or r64 are
filled with zeros.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:reg (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 50 /r MOVMSKPS reg,
xmm
AValid Valid Extract 4-bit sign mask from
xmm and store in reg. The
upper bits of r32 or r64 are
filled with zeros.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:reg (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 38 2A /r MOVNTDQA
xmm1, m128
AValid Valid Move double quadword
from m128 to xmm using
non-temporal hint if WC
memory type.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA