Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 9
Documentation Changes
Documentation Changes
1. Updates to Chapter 3, Volume 2A
Change bars show changes to Chapter 3 of the Intel
®
64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A: Instruction Set Reference, A-M.
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3.1.1 Instruction Format
The following is an example of the format used for each instruction description in this
chapter. The heading below introduces the example. The table below provides an
example summary table.
CMC—Complement Carry Flag [this is an example]
Instruction Operand Encoding
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3.1.1.3 Operand Encoding Column in the Instruction Summary Table
The “operand encoding” column is abbreviated as Op/En in the Instruction Summary
table heading. Instruction operand encoding information is provided for each assembly
instruction syntax using a letter to cross reference to a row entry in the operand
encoding definition table that follows the instruction summary table. The definition table
is organized according to the order of operand in Intel assembly syntax. The encoding
method for each operand in the instruction byte stream is expressed via modR/M:reg,
modR/M:r/m, imm8/16/32/64, etc (cross reference).
NOTES
• The letters in the Op/En column of an instruction apply ONLY to the
encoding definition table immediately following the instruction
summary table.
• In the encoding definition table, the letter ‘r’ within a pair of
parenthesis denotes the content of the operand will be read by the
processor. The letter ‘w’ within a pair of parenthesis denotes the
content of the operand will be updated by the processor.
Opcode Instruction Op/En 64-bit
Mode
Compat/
Leg Mode
Description
F5 CMC A Valid Valid Complement carry flag.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA