Specifications
Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 89
Documentation Changes
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
A1 MOV AX,moffs16* C Valid Valid Move word at (seg:offset) to
AX.
A1 MOV
EAX,moffs32*
CValid Valid Move doubleword at
(seg:offset) to EAX.
REX.W + A1 MOV
RAX,moffs64*
C Valid N.E. Move quadword at (offset)
to RAX.
A2 MOV moffs8,AL D Valid Valid Move AL to (seg:offset).
REX.W + A2 MOV moffs8
***
,AL D Valid N.E. Move AL to (offset).
A3 MOV moffs16*,AX D Valid Valid Move AX to (seg:offset).
A3 MOV
moffs32*,EAX
DValid Valid Move EAX to (seg:offset).
REX.W + A3 MOV
moffs64*,RAX
DValid N.E. Move RAX to (offset).
B0+ rb MOV r8, imm8 EValid Valid Move imm8 to r8.
REX + B0+ rb MOV r8
***
, imm8 EValid N.E. Move imm8 to r8.
B8+ rw MOV r16, imm16 EValid Valid Move imm16 to r16.
B8+ rd MOV r32, imm32 EValid Valid Move imm32 to r32.
REX.W + B8+ rd MOV r64, imm64 EValid N.E. Move imm64 to r64.
C6 /0 MOV r/m8, imm8 FValid Valid Move imm8 to r/m8.
REX + C6 /0 MOV r/m8***,
imm8
FValid N.E. Move imm8 to r/m8.
C7 /0 MOV r/m16,
imm16
FValid Valid Move imm16 to r/m16.
C7 /0 MOV r/m32,
imm32
FValid Valid Move imm32 to r/m32.
REX.W + C7 /0 MOV r/m64,
imm32
FValid N.E. Move imm32 sign extended
to 64-bits to r/m64.
NOTES:
*The moffs8, moffs16, moffs32 and moffs64 operands specify a simple offset relative to the
segment base, where 8, 16, 32 and 64 refer to the size of the data. The address-size attribute
of the instruction determines the size of the offset, either 16, 32 or 64 bits.
**In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction
(see the following “Description” section for further information).
***In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.