Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 86
Documentation Changes
any serializing instructions (such as the CPUID instruction). MFENCE does not serialize
the instruction stream.
Weakly ordered memory types can be used to achieve higher processor performance
through such techniques as out-of-order issue, speculative reads, write-combining, and
write-collapsing. The degree to which a consumer of data recognizes or knows that the
data is weakly ordered varies among applications and may be unknown to the producer
of this data. The MFENCE instruction provides a performance-efficient way of ensuring
load and store ordering between routines that produce weakly-ordered results and
routines that consume that data.
Processors are free to fetch and cache data speculatively from regions of system
memory that use the WB, WC, and WT memory types. This speculative fetching can
occur at any time and is not tied to instruction execution. Thus, it is not ordered with
respect to executions of the MFENCE instruction; data can be brought into the caches
speculatively just before, during, or after the execution of an MFENCE instruc-
tion.Processors are free to fetch and cache data speculatively from regions of system
memory that use the WB, WC, and WT memory types. This speculative fetching can
occur at any time and is not tied to instruction execution. Thus, it is not ordered with
respect to executions of the MFENCE instruction; data can be brought into the caches
speculatively just before, during, or after the execution of an MFENCE instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
...
MINPD—Return Minimum Packed Double-Precision Floating-Point Values
Instruction Operand Encoding
...
1. A load instruction is considered to become globally visible when the value to be loaded into its desti-
nation register is determined.
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 5D /r MINPD xmm1,
xmm2/m128
A Valid Valid Return the minimum double-
precision floating-point
values between
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA