Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 85
Documentation Changes
MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value
Instruction Operand Encoding
...
MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value
Instruction Operand Encoding
...
MFENCE—Memory Fence
Instruction Operand Encoding
Description
Performs a serializing operation on all load-from-memory and store-to-memory instruc-
tions that were issued prior the MFENCE instruction. This serializing operation guaran-
tees that every load and store instruction that precedes the MFENCE instruction in
program order becomes globally visible before any load or store instruction that follows
the MFENCE instruction.
1
The MFENCE instruction is ordered with respect to all load and
store instructions, other MFENCE instructions, any LFENCE and SFENCE instructions, and
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 5F /r MAXSD xmm1,
xmm2/m64
A Valid Valid Return the maximum scalar
double-precision floating-
point value between
xmm2/mem64 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 5F /r MAXSS xmm1,
xmm2/m32
A Valid Valid Return the maximum scalar
single-precision floating-
point value between
xmm2/mem32 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F AE /6 MFENCE A Valid Valid Serializes load and store
operations.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA