Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 83
Documentation Changes
LTR—Load Task Register
Instruction Operand Encoding
...
MASKMOVDQU—Store Selected Bytes of Double Quadword
Instruction Operand Encoding
Description
Stores selected bytes from the source operand (first operand) into an 128-bit memory
location. The mask operand (second operand) selects which bytes from the source
operand are written to memory. The source and mask operands are XMM registers. The
location of the first byte of the memory location is specified by DI/EDI and DS registers.
The memory location does not need to be aligned on a natural boundary. (The size of the
store address depends on the address-size attribute.)
The most significant bit in each byte of the mask operand determines whether the corre-
sponding byte in the source operand is written to the corresponding byte location in
memory: 0 indicates no write and 1 indicates write.
The MASKMOVDQU instruction generates a non-temporal hint to the processor to mini-
mize cache pollution. The non-temporal hint is implemented by using a write combining
(WC) memory type protocol (see “Caching of Temporal vs. Non-Temporal Data” in
Chapter 10, of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual,
Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model,
a fencing operation implemented with the SFENCE or MFENCE instruction should be used
in conjunction with MASKMOVDQU instructions if multiple processors might use different
memory types to read/write the destination memory locations.
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 00 /3 LTR r/m16 A Valid Valid Load r/m16 into task
register.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F F7 /r MASKMOVDQU
xmm1, xmm2
A Valid Valid Selectively write bytes from
xmm1 to memory location
using the byte mask in
xmm2. The default memory
location is specified by
DS:EDI.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r) ModRM:r/m (r) NA NA