Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 79
Documentation Changes
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register
Instruction Operand Encoding
...
LLDT—Load Local Descriptor Table Register
Instruction Operand Encoding
...
LMSW—Load Machine Status Word
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01 /2 LGDT m16&32 A N.E. Valid Load m into GDTR.
0F 01 /3 LIDT m16&32 A N.E. Valid Load m into IDTR.
0F 01 /2 LGDT m16&64 AValid N.E. Load m into GDTR.
0F 01 /3 LIDT m16&64 AValid N.E. Load m into IDTR.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 00 /2 LLDT r/m16 A Valid Valid Load segment selector
r/m16 into LDTR.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01 /6 LMSW r/m16 A Valid Valid Loads r/m16 in machine
status word of CR0.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA