Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 76
Documentation Changes
LDDQU—Load Unaligned Integer 128 Bits
Instruction Operand Encoding
...
LDMXCSR—Load MXCSR Register
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F F0 /r LDDQU xmm1,
mem
A Valid Valid Load unaligned data from
mem and return double
quadword in xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F,AE,/2 LDMXCSR m32 A Valid Valid Load MXCSR register from
m32.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA