Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 75
Documentation Changes
LAHF—Load Status Flags into AH Register
Instruction Operand Encoding
...
LAR—Load Access Rights Byte
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
9F LAHF A Invalid* Valid Load: AH ←
EFLAGS(SF:ZF:0:AF:0:PF:1:CF).
NOTES:
*Valid in specific steppings. See Description section.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 02 /r LAR r16, r16/m16 AValid Valid r16 ← r16/m16 masked by
FF00H.
0F 02 /r LAR r32,
r32/m16
1
AValid Valid r32 ← r32/m16 masked by
00FxFF00H
REX.W + 0F 02
/r
LAR r64,
r32/m16
1
AValid N.E. r64 ← r32/m16 masked by
00FxFF00H and zero
extended
NOTES:
1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are
ignored.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA