Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 68
Documentation Changes
INVD—Invalidate Internal Caches
Instruction Operand Encoding
...
INVLPG—Invalidate TLB Entry
Instruction Operand Encoding
...
IRET/IRETD—Interrupt Return
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 08 INVD A Valid Valid Flush internal caches;
initiate flushing of external
caches.
NOTES:
* See the IA-32 Architecture Compatibility section below.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01/7 INVLPG m A Valid Valid Invalidate TLB Entry for
page that contains m.
NOTES:
* See the IA-32 Architecture Compatibility section below.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
CF IRET A Valid Valid Interrupt return (16-bit
operand size).
CF IRETD A Valid Valid Interrupt return (32-bit
operand size).
REX.W + CF IRETQ A Valid N.E. Interrupt return (64-bit
operand size).
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA