Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 64
Documentation Changes
Instruction Operand Encoding
...
INS/INSB/INSW/INSD—Input from Port to String
Instruction Operand Encoding
...
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r, w) NA NA NA
B reg (r, w) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
6C INS m8, DX A Valid Valid Input byte from I/O port
specified in DX into memory
location specified in ES:(E)DI
or RDI.*
6D INS m16, DX A Valid Valid Input word from I/O port
specified in DX into memory
location specified in ES:(E)DI
or RDI.
1
6D INS m32, DX A Valid Valid Input doubleword from I/O
port specified in DX into
memory location specified in
ES:(E)DI or RDI.
1
6C INSB A Valid Valid Input byte from I/O port
specified in DX into memory
location specified with
ES:(E)DI or RDI.
1
6D INSW A Valid Valid Input word from I/O port
specified in DX into memory
location specified in ES:(E)DI
or RDI.
1
6D INSD A Valid Valid Input doubleword from I/O
port specified in DX into
memory location specified in
ES:(E)DI or RDI.
1
NOTES:
* In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit
mode, only 32-bit (EDI) and 16-bit (DI) address sizes are supported.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA