Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 62
Documentation Changes
IMUL—Signed Multiply
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F6 /5 IMUL r/m8* AValid Valid AX← AL ∗ r/m byte.
F7 /5 IMUL r/m16 AValid Valid DX:AX ← AX ∗ r/m word.
F7 /5 IMUL r/m32 AValid Valid EDX:EAX ← EAX ∗ r/m32.
REX.W + F7 /5 IMUL r/m64 A Valid N.E. RDX:RAX ← RAX ∗ r/m64.
0F AF /r IMUL r16, r/m16 BValid Valid word register ← word
register ∗ r/m16.
0F AF /r IMUL r32, r/m32 B Valid Valid doubleword register ←
doubleword register ∗
r/m32.
REX.W + 0F AF
/r
IMUL r64, r/m64 B Valid N.E. Quadword register ←
Quadword register ∗ r/m64.
6B /r ib IMUL r16, r/m16,
imm8
CValid Valid word register ← r/m16 ∗
sign-extended immediate
byte.
6B /r ib IMUL r32, r/m32,
imm8
C Valid Valid doubleword register
←
r/m32 ∗ sign-extended
immediate byte.
REX.W + 6B /r ib IMUL r64, r/m64,
imm8
C Valid N.E. Quadword register ← r/m64
∗ sign-extended immediate
byte.
69 /r iw IMUL r16, r/m16,
imm16
CValid Valid word register ← r/m16 ∗
immediate word.
69 /r id IMUL r32, r/m32,
imm32
C Valid Valid doubleword register ←
r/m32 ∗ immediate
doubleword.
REX.W + 69 /r id IMUL r64, r/m64,
imm32
C Valid N.E. Quadword register ← r/m64
∗ immediate doubleword.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r, w) NA NA NA
B ModRM:reg (r, w) ModRM:r/m (r) NA NA
C ModRM:reg (r, w) ModRM:r/m (r) imm8/16/32 NA