Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 61
Documentation Changes
Instruction Operand Encoding
...
IDIV—Signed Divide
Instruction Operand Encoding
...
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F6 /7 IDIV r/m8 A Valid Valid Signed divide AX by r/m8,
with result stored in: AL ←
Quotient, AH ← Remainder.
REX + F6 /7 IDIV r/m8* A Valid N.E. Signed divide AX by r/m8,
with result stored in AL ←
Quotient, AH ← Remainder.
F7 /7 IDIV r/m16 A Valid Valid Signed divide DX:AX by
r/m16, with result stored in
AX ← Quotient, DX ←
Remainder.
F7 /7 IDIV r/m32 A Valid Valid Signed divide EDX:EAX by
r/m32, with result stored in
EAX ← Quotient, EDX ←
Remainder.
REX.W + F7 /7 IDIV r/m64 A Valid N.E. Signed divide RDX:RAX by
r/m64, with result stored in
RAX ← Quotient, RDX ←
Remainder.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA