Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 58
Documentation Changes
EXTRACTPS — Extract Packed Single Precision Floating-Point Value
Instruction Operand Encoding
...
FSAVE/FNSAVE—Store x87 FPU State
...
IA-32 Architecture Compatibility
For Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAIT
instruction should be executed before attempting to read from the memory image stored
with a prior FSAVE/FNSAVE instruction. This FWAIT instruction helps ensure that the
storage operation has been completed.
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is
possible (under unusual circumstances) for an FNSAVE instruction to be interrupted prior
to being executed to handle a pending FPU exception. See the section titled “No-Wait
FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel
®
64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these
circumstances. An FNSAVE instruction cannot be interrupted in this way on a Pentium 4,
Intel Xeon, or P6 family processor.
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 3A 17
/r ib
EXTRACTPS
reg/m32, xmm2,
imm8
AValid Valid Extract a single-precision
floating-point value from
xmm2 at the source offset
specified by imm8 and store
the result to reg or m32.
The upper 32 bits of r64 is
zeroed if reg is r64.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) ModRM:reg (r) imm8 NA