Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 56
Documentation Changes
Instruction Operand Encoding
...
DIVSS—Divide Scalar Single-Precision Floating-Point Values
Instruction Operand Encoding
...
DPPD — Dot Product of Packed Double Precision Floating-Point Values
Instruction Operand Encoding
...
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 5E /r DIVSS xmm1,
xmm2/m32
A Valid Valid Divide low single-precision
floating-point value in
xmm1 by low single-
precision floating-point
value in xmm2/m32.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 3A 41 /r
ib
DPPD xmm1,
xmm2/m128,
imm8
A Valid Valid Selectively multiply packed
DP floating-point values
from xmm1 with packed DP
floating-point values from
xmm2, add and selectively
store the packed DP
floating-point values to
xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) imm8 NA