Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 55
Documentation Changes
Instruction Operand Encoding
...
DIVPD—Divide Packed Double-Precision Floating-Point Values
Instruction Operand Encoding
...
DIVPS—Divide Packed Single-Precision Floating-Point Values
Instruction Operand Encoding
...
DIVSD—Divide Scalar Double-Precision Floating-Point Values
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (w) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 5E /r DIVPD xmm1,
xmm2/m128
A Valid Valid Divide packed double-
precision floating-point
values in xmm1 by packed
double-precision floating-
point values xmm2/m128.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 5E /r DIVPS xmm1,
xmm2/m128
A Valid Valid Divide packed single-
precision floating-point
values in xmm1 by packed
single-precision floating-
point values xmm2/m128.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 5E /r DIVSD xmm1,
xmm2/m64
A Valid Valid Divide low double-precision
floating-point value n xmm1
by low double-precision
floating-point value in
xmm2/mem64.