Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 52
Documentation Changes
CVTTSD2SI—Convert with Truncation Scalar Double-Precision FP Value to
Signed Integer
Instruction Operand Encoding
...
CVTTSS2SI—Convert with Truncation Scalar Single-Precision FP Value to
Dword Integer
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 2C /r CVTTSD2SI r32,
xmm/m64
A Valid Valid Convert one double-
precision floating-point
value from xmm/m64 to
one signed doubleword
integer in r32 using
truncation.
F2 REX.W 0F 2C
/r
CVTTSD2SI r64,
xmm/m64
A Valid N.E. Convert one double
precision floating-point
value from xmm/m64 to
one signedquadword
integer in r64 using
truncation.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 2C /r CVTTSS2SI r32,
xmm/m32
A Valid Valid Convert one single-precision
floating-point value from
xmm/m32 to one signed
doubleword integer in r32
using truncation.
F3 REX.W 0F 2C
/r
CVTTSS2SI r64,
xmm/m32
A Valid N.E. Convert one single-precision
floating-point value from
xmm/m32 to one signed
quadword integer in r64
using truncation.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA