Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 43
Documentation Changes
CRC32 — Accumulate CRC32 Value
Instruction Operand Encoding
...
CVTDQ2PD—Convert Packed Dword Integers to Packed Double-Precision
FP Values
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 38 F0 /r CRC32 r32, r/m8 A Valid Valid Accumulate CRC32 on r/m8.
F2 REX 0F 38
F0 /r
CRC32 r32, r/m8* A Valid N.E. Accumulate CRC32 on r/m8.
F2 0F 38 F1 /r CRC32 r32, r/m16 A Valid Valid Accumulate CRC32 on
r/m16.
F2 0F 38 F1 /r CRC32 r32, r/m32 A Valid Valid Accumulate CRC32 on
r/m32.
F2 REX.W 0F 38
F0 /r
CRC32 r64, r/m8 A Valid N.E. Accumulate CRC32 on r/m8.
F2 REX.W 0F 38
F1 /r
CRC32 r64, r/m64 A Valid N.E. Accumulate CRC32 on
r/m64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F E6 CVTDQ2PD xmm1,
xmm2/m64
A Valid Valid Convert two packed signed
doubleword integers from
xmm2/m128 to two packed
double-precision floating-
point values in xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA