Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 42
Documentation Changes
Table 3-20. Information Returned by CPUID Instruction (Continued)
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Table 3-24. More on Feature Information Returned in the EDX Register
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Initial EAX
Value Information Provided about the Processor
Basic CPUID Information
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80000001H EAX
EBX
ECX
Extended Processor Signature and Feature Bits.
Reserved
Bit 0: LAHF/SAHF available in 64-bit mode
Bits 31-1 Reserved
EDX Bits 10-0: Reserved
Bit 11: SYSCALL/SYSRET available (when in 64-bit mode)
Bits 19-12: Reserved = 0
Bit 20: Execute Disable Bit available
Bits 25-21: Reserved = 0
Bit 26: 1-GByte pages are available if 1
Bit 27: RDTSCP and IA32_TSC_AUX are available if 1
Bits 28: Reserved = 0
Bit 29: Intel
®
64 Architecture available if 1
Bits 31-30: Reserved = 0
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Bit # Mnemonic Description
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13 PGE Page Global Bit. The global bit is supported in paging-structure entries that
map a page, indicating TLB entries that are common to different processes
and need not be flushed. The CR4.PGE bit controls this feature.
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