Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 40
Documentation Changes
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes
Instruction Operand Encoding
...
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values
and Set EFLAGS
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F C7 /1 m64 CMPXCHG8B m64 A Valid Valid* Compare EDX:EAX with
m64. If equal, set ZF and
load ECX:EBX into m64. Else,
clear ZF and load m64 into
EDX:EAX.
REX.W + 0F C7
/1 m128
CMPXCHG16B
m128
A Valid N.E. Compare RDX:RAX with
m128. If equal, set ZF and
load RCX:RBX into m128.
Else, clear ZF and load m128
into RDX:RAX.
NOTES:
*See IA-32 Architecture Compatibility section below.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r, w) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 2F /r COMISD xmm1,
xmm2/m64
A Valid Valid Compare low double-
precision floating-point
values in xmm1 and
xmm2/mem64 and set the
EFLAGS flags accordingly.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r) ModRM:r/m (r) NA NA