Specifications

Intel

64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 38

Documentation Changes

CMPSS—Compare Scalar Single-Precision Floating-Point Values

Instruction Operand Encoding

Description

Compares the low single-precision floating-point values in the source operand (second

operand) and the destination operand (first operand) and returns the results of the

comparison to the destination operand. The comparison predicate operand (third

operand) specifies the type of comparison performed. The comparison result is a double-

word mask of all 1s (comparison true) or all 0s (comparison false).

The source operand can be an XMM register or a 32-bit memory location. The destination

operand is an XMM register. The result is stored in the low doubleword of the destination

operand; the 3 high-order doublewords remain unchanged. The comparison predicate

operand is an 8-bit immediate, the first 3 bits of which define the type of comparison to

be made (see Table 3-15). Bits 3 through 7 of the immediate are reserved.

The unordered relationship is true when at least one of the two source operands being

compared is a NaN; the ordered relationship is true when neither source operand is a

NaN

A subsequent computational instruction that uses the mask result in the destination

operand as an input operand will not generate a fault, since a mask of all 0s corresponds

to a floating-point value of +0.0 and a mask of all 1s corresponds to a QNaN.

Some of the comparisons listed in Table 3-15 can be achieved only through software

emulation. For these comparisons the program must swap the operands (copying regis-

ters when necessary to protect the data that will now be in the destination operand), and

then perform the compare using a different predicate. The predicate to be used for these

emulations is listed in Table 3-15 under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops in

addition to the three-operand CMPSS instruction. See Table 3-19.

...

Opcode Instruction Op/

64-Bit

Mode

Compat/

Leg Mode

Description

F3 0F C2 /r ib CMPSS xmm1,

xmm2/m32, imm8

A Valid Valid Compare low single-

precision floating-point

value in xmm2/m32 and

xmm1 using imm8 as

comparison predicate.

Op/En Operand 1 Operand 2 Operand 3 Operand 4

A ModRM:reg (r, w) ModRM:r/m (r) imm8 NA